JPH0282335A - Bus controller - Google Patents

Abstract

PURPOSE:To perform fault recovery by measuring the processing time of a bus master to detect its abnormality and transferring the control to another normal bus master. CONSTITUTION:When a bus master 3 gets the control right of a bus 17 to start the control of the bus 17, a timer 5 starts counting. When the bus master 3 does not terminate the control of the bus 17 after a normal processing time elapses, the timer 5 terminates counting of a preliminarily determined prescribed time to judge the bus master 3 to be abnormal, and a hold signal line 12 is forcibly invalidated through a gate 7 to deprive the bus master 3 of the control right of the bus 17. Further, a main bus master 2 is interrupted through a signal INT line 15. The main bus master 2 gets the control right of the bus 17 instead of the bus master 3 where abnormality occurs. Thus, an interruption handling program for fault recovery is started, and the main bus master 2 discriminates the cause of abnormality to perform a proper processing, and the operation of a system is continued.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a bus control device, and particularly to a bus control device suitable for application to a multipath master system of a microcomputer system.

(Prior Art) Conventionally, in many microcomputer systems, processing for abnormality monitoring is regularly executed. For example, the microprocessor resets the watchdog timer periodically, and if the microprocessor does not reset the watchdog timer for a certain period of time, it is determined that access to the microprocessor has been interrupted due to some abnormality. There is a known method for recovering the microprocessor by using a method such as initializing the microprocessor.

(Problems to be Solved by the Invention) Since the conventional microcomputer system is configured as described above, it is necessary to waste CPU time for abnormality monitoring, and it is necessary to have multiple bus masters. The reality is that there is no method for monitoring abnormalities in multipath master systems. For example, when a bus master other than a microprocessor controls the bus, even if an abnormality occurs in the bus master, it cannot be detected.

The present invention has been made in view of the above, and its purpose is to:
To obtain a bus control device capable of realizing failure recovery by detecting an abnormality by measuring processing time of a bus master and transferring control to another normal bus master.

[Structure of the invention]

(Means for Solving the Problems) A bus control device of the present invention includes at least one first bus master that controls a bus: controls the bus, and also performs abnormality recovery processing of the first bus master. means for selectively assigning each of the first and second bus masters to control the bus; means provided for each first bus master to perform maximum processing when the corresponding first bus master operates normally; a clocking means for which a set time longer than the current bus master is set and starts operating when the corresponding first bus master starts processing; an interrupt control means for issuing an interrupt for abnormal processing to the second bus master;
It is configured as having the following.

(Function) The clock means monitors whether the first bus master is operating normally. If a set time exceeding the normal processing time has elapsed since the first bus master started bus control, the operation of the second bus master is regulated by the interrupt control means based on the output from the timer. Interrupts the second bus master to control the bus and handle abnormalities.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

The drawing is a block diagram of a bus control device according to an embodiment of the present invention. As shown in the figure, the bus arbiter 1 includes a main bus master 2 and a bus master 3 that control buses 17 such as a data bus, an address bus, and a control bus.
It has a function of arbitrating which of the bus masters 4 and 4 controls the bus 17. Here, the main bus master 2 performs central control in the system and also performs processing for recovering from an abnormality. When the control time of the bus 7 by the bus master 3 is longer than a preset specified value, the timer 5 determines that there is an abnormality, releases the bus 17, and outputs an interrupt to the main bus master 2. When the control time of the bus 17 by the bus master 4 is longer than a preset specified value, the timer 6 determines that there is an abnormality, releases the bus 17, and outputs an interrupt to the main bus master 2. In addition,
bus arbiter] and main bus master 2.
A signal line 9 and a HOLD signal line 10 are connected. H
The LDA signal line 9 sends a signal indicating that the main bus master 2 has released the bus 17 to the bus arbiter 1, and the HOL
The D signal line 10 is connected from the bus arbiter 1 to the main bus master 2.
A signal requesting release of the bus 17 is sent to the bus 17. Further, an HLDA signal line 11, a HOLD signal line 12, an HLDA signal line 13, and a HOLD signal line 14 are led out from the bus arbiter 1. The HLDA signal line 11 sends a signal that allows the bus master 3 to control the bus 17, and the HOLD signal line 12 sends a signal that allows the bus master 3 to control the bus 17 to the bus arbiter 1.
A signal requesting control of 7 is sent. Further, the HLDA signal line 13 sends out a signal that allows the bus master 4 to control the bus 17, and the HOLD signal line 14 sends out a signal that the bus master 4 requests the bus arbiter 1 to control the bus 17. Further, an INT signal line 15 is installed between the main bus master 2 and the timer 5, and an INT signal line 16 is installed between the main bus master 2 and the timer 6. INT
The signal line 15 sends a signal from the timer 5 to the main bus master 2 to interrupt the CPU of the main bus master 2, and starts a program for recovery from the failure. IN
The T signal line 16 sends a signal for interrupting the CPU of the main bus master 2 from the timer 6 to the main bus master 2, and starts a program for recovery from the failure. The gate 7 is provided on the HOLD signal line 12 interposed between the bus master 3 and the bus arbiter 1, and is
It acts when invalidating the signal on the LD signal line 12. On the other hand, the gate 8 is provided on the HOLD signal line 14 interposed between the bus master 4 and the bus arbiter 1, and acts when the timer 6 invalidates the signal on the HOLD signal line 4.

The operation of the configuration as described above will now be explained.

The normal processing times of bus master 3 and bus master 4 are known in advance, and these times are the basis of the specified times for timers 5 and 6.

That is, the timer 5 and the timer 6 are set to have a specified time for abnormality determination to be slightly longer than the normal processing time of the bus master 3 and the bus master 4.

Assume that the main bus master 2 is currently controlling the bus 17. Next, the bus master 3 holds the HOLD signal line 1
2 requests the main bus master 2 to pass the signal on the bus 17 via the bus arbiter 1 and the HOLD signal line 10, and the main bus master 2 completes the process being executed and transfers the signal from the HLDA signal line 9 to the main bus master 2. Control of the bus 17 is permitted to the bus master 3 via the bus arbiter 1 and the HLDA signal line 11. In this way, bus master 3
At the same time that the bus 17 gains control and starts controlling the bus 17, the timer 5 starts measuring time. If the bus master 3 does not finish controlling the bus 17 even after the normal processing time has elapsed, the timer 5 will count the predetermined time and determine that there is an abnormality, and force the HOLD signal line 12 through the gate 7. The main bus master 2 is invalidated to take control of the bus 17 from the bus master 3, and further interrupts the main bus master 2 through the INT signal line 15. Main bus master 2
takes control of the bus 17 in place of the bus master 3 that has caused the abnormality, and starts an interrupt processing program for recovery from the failure. Using this program, the main bus master 2 determines the cause of the abnormality, performs appropriate processing, and continues the operation of the system.

Even when control of the bus 17 is transferred from the main bus master 2 to the bus master 4, the timer 6 determines whether the bus master 4 completes the processing within a specified time in exactly the same manner. If it is determined to be abnormal, timer 6 outputs an IN signal.
An interrupt is applied to the main bus master 2 through the T signal line 16, and a fault recovery program by the main bus master 2 is activated.

Through the operations described above, even after control of the bus 17 is transferred from main bus master 2 to bus master 3 or bus master 4, the operation is monitored by timer 5 or timer 6, and if an abnormality is detected, the main bus master is notified by an interrupt. 2 returns control over the bus 17, starts an abnormality recovery program, investigates the cause of the abnormal operation, and executes appropriate processing to continue the operation of the system.

〔Effect of the invention〕

According to the present invention, it is possible for a multipath master system to self-recover in the event of a system error, and even if an abnormal bus master occurs, it is possible to release this bus master from control and continue bus control by the remaining bus masters, and parallel It is possible to detect and deal with a processing system that has performed an abnormal operation in the processing system, and the reliability of the multipath master system can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bus control device according to an embodiment of the present invention. 1... Bus arbiter, 2... Main bus master, 3
．． 4...Pasta, 5,6...Timer, 7.8...
Gate. Applicant's agent Mr. Sato

Claims (1)

[Claims] at least one first bus master that controls the bus; a second bus master that controls the bus and performs abnormality recovery processing for the first bus master;
means for selectively assigning each bus master to control the bus; provided for each first bus master, a set time longer than the maximum processing time when the corresponding first bus master operates normally; A timer that starts operating when the first bus master starts processing; and an interrupt control that regulates the operation of the corresponding first bus master based on the output of the timer and interrupts the second bus master for abnormal processing. A bus control device comprising means and;