JPS603778A - Processor reset system - Google Patents

Abstract

PURPOSE:To reset an abnormal processor without the influence upon the other processors when the processor becomes abnormal, by providing a communication right control part, a timer, a processor operation state monitor means, etc. CONSTITUTION:When a subprocessor 2 performs communication, it outputs a communication right request signal to a communication right control circuit 6. The circuit 6 gives the communication right to the processor 2, and then, a timer circuit 7 is started. In this case, if an abnormality occurs in the processor 2, the circuit 6 cancels the permission of the communication right given to the processor 2 through the circuit 7. A main processor 1 outputs an operation state reporting command to processors 2, 3, etc. successively from its operation monitor part 1-0, and processors 2, 3, etc. report operation states. However, the processor where an abnormality occurs does not report the operation state, and the processor 1 outputs a reset signal to this processor to reset it. The circuit 1-0, the circuit 7, etc. are provided to reset the processor, where an abnormality occurs, without exerting the influence upon the other processors when an abnormality occurs in the processor.

Description

[Detailed description of the invention] [Technical field of invention] The present invention is constituted by a plurality of processors.

The present invention relates to a processor reset method that detects an abnormality in a processor through inter-processor communication when communicating between processors, and resets the processor in which the abnormality has occurred.

[Prior art and problems]

For example, as shown in FIG. CPU1.

Consisting of CPU2, ... CPUn, each CPU0
In a device that performs data processing by communicating with each other between CPUs 0 to n, the CPUs 0 to n perform data processing by sharing functions, respectively. In this case, a communication right control circuit C is provided to prevent contention on bus B when communicating between CPUs, and when a user wants to use bus B, this communication right control circuit C grants permission to the CPU that has requested the use of bus B. give. If the CPU that has been given permission to use this communication completes normally, it will send a completion report to the communication right control circuit C, but if an abnormality occurs in the CPU that has been given permission to use it, a normal communication completion signal will be returned. This means that other CPUs are not connected to bus B.
Because you will not be able to use it.

The communication right control circuit C is provided with a timer, and when a normal communication end report is not returned after a certain period of time, the previous usage permission is canceled and the communication right is granted to another CPU.

Conventionally, when such an abnormality occurs, the abnormality is detected for each processor, and only the CPU in which the abnormality has occurred is reset.

There is a method that resets all processors no matter which processor detects an error.

However, in the former case, the processor is initialized by a reset, causing a difference in state from other processors, and this reset state is not reported to other processors, making it difficult to match the states, which causes problems in data processing. be.

In the latter case, there is a problem in that the entire device is initialized, and even normal operations up to that point are interrupted.

[Purpose of the invention]

The purpose of the present invention is to improve the above problems.

In such devices that perform data processing without communicating between multiprocessors, the communication right permission is automatically dropped after a certain period of time has passed after a communication right permission request occurs, and the central Processor reset: A processor is installed to monitor the operation of other processors, and when an abnormality is detected, only that processor is reset, and the reset processor is recognized so that other normal processors are not affected. The purpose is to provide a method.

[Structure of the invention]

In order to achieve this object, in the processor reset method of the present invention, in a data processing device that has a plurality of processors and performs inter-processor communication, a communication right control unit that grants communication rights to the processors and a timer means are provided. One of the processors is provided with an operating state monitoring means for monitoring the operating state of the other processor, and a time limit is set for the use of the communication right granted by the communication right control section, and when the time limit is exceeded, the authorized communication right is used. and the processor having the operating state monitoring means periodically monitors and controls the operation of other processors to detect the presence or absence of abnormality therein;
The present invention is characterized in that the processor is reset when an abnormality is detected.

[Embodiments of the invention]

An embodiment of the present invention will be described based on FIG.

In the figure, 1 is a main processor having an operation monitoring section 1-0, which will be described later, and 2, 3, . . . 4 are sub-processors.

5 is a communication circuit, 6 is a communication right control circuit, 7 is a timer circuit,
8-1 to 8-n are AND gates.

The main processor 1 performs data processing together with sub-processors 2, 3...4, etc.
. . 4 has a function of monitoring the operating state of the controller 4 and controlling the data processing state accordingly. In order to monitor the above-mentioned operating states, operating state reporting commands are sequentially output to the sub-processors 2, 3, . . . , 4. If the sub-processors 2, 3, . . . 4 are in a normal operating state, a response will be made.

It does not respond in case of abnormality. Therefore, the operation monitoring unit 1-0
Since it has a built-in counter and a reset signal output circuit, if there is no response even after sending the above operating status report command to a specific sub-processor a specified number of times, it outputs a reset signal to the sub-processor and outputs a reset signal to the sub-processor. Reset.

The communication circuit 5 is connected to the main processor 1. Sub-processor 2, 3...
・It performs communication between each processor such as No. 4.

The communication right control circuit 6 grants communication rights to a specific processor when communication requests conflict among the processors.

The timer circuit 7 is for forcibly dropping the granted communication right when an abnormality occurs in the processor to which the communication right has been granted and there is no completion report. This is reset when communication rights are granted.

Next, the operation of the present invention will be explained with reference to FIG.

(1) When the sub-processor 2 now communicates, the sub-processor 2 outputs a communication right request signal to the communication right control circuit 6 via the AND gate 8-2.

At this time, the other terminal of the AND gate 8-2 has "0".
'' is being applied, the AND gate 8-2 is in an on state, and the above signal is transmitted to the communication right control circuit 6. When the communication circuit 5 is not being used by another processor, the communication right control circuit 6 grants communication right to the processor, and the timer circuit 7 is thereby activated. If the sub-processor 2 normally completes the communication, this is transmitted to the communication right control circuit 6, so that the communication right control circuit 6 resets the timer circuit 7.

(2) However, when an abnormality occurs in the sub-processor 2 to which the above communication permission has been granted, the timer circuit 7 outputs "1" to the AND gate 8-2 after a certain period of time and turns it off. do. As a result, the communication right control circuit 6 can drop the communication right granted to the sub-processor 2.

(3) By the way, the main processor 1 has its operation monitoring unit 1-0
The operating state report command is sequentially outputted to each of the sub-processors 2, 3, . . . , 4. If the subprocessors 2, 3, . . . , 4 receive this operating state report command, they will report the normal operating state if they are in a normal operating state, but if they are in an abnormal state, this report will not be made. Therefore, the main processor 1 uses its built-in counter to check the presence or absence of this report for each sub-processor, so if there is no report of normal operation status for a certain number of consecutive times, it sends a reset signal to that sub-processor. At the same time, a reset signal is sent to the timer circuit 7, and if the timer circuit for the sub-processor is activated, it is also reset. Therefore, the above (2
), if an abnormal state occurs in the sub-processor 2, the main processor 1 will detect the abnormality in the sub-processor 2 in this way, and the sub-processor 2 will be reset.

Therefore, since main processor 1 recognizes that sub-processor 2 is in the reset state,
Even if data processing is continued in , a command to perform the next data processing is not output.

(4) If an abnormality occurs in the main processor 1 when the communication right is granted to the main processor 1, the timer circuit 7 outputs "1" after a specified time.

This turns off the AND gate 8-1.

The communication right to this main processor 1 is forcibly dropped, and the timer circuit 7 outputs "
1'' acts as a reset signal for the main processor 1 and resets the main processor 1.

〔Effect of the invention〕

According to the present invention, in a data processing device configured with a plurality of processors, even if an abnormality occurs in one processor, the processor in which the abnormality has occurred can be reset without affecting the other processors, so that the state of each processor is inconsistent. can be effectively prevented.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional data processing apparatus having a plurality of processors, and FIG. 2 is a configuration diagram of an embodiment of the present invention. In the figure, 1 is a main processor, and 1-0 is an operation monitoring unit. 2.3...4 are sub-processors, 5 is a communication circuit, 6 is a communication right control circuit, 7 is a timer circuit, and 8-1 to 8-n are AND gates. Patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani

Claims (1)

[Scope of Claims] A data processing device having a plurality of processors and performing inter-processor communication is provided with a communication right control section for granting communication rights to the processors, a timer means, and one of the processors is provided with a communication right control section for granting communication rights to the processors. An operating state monitoring means for monitoring the operating state is provided, and a time limit is set for the use of the communication right permitted by the communication right control section, and when the time limit is exceeded, the permitted communication right is denied, and the above operating state monitoring means is provided. A processor having means periodically monitors and controls the operations of other processors to detect the presence or absence of an abnormality. A processor reset method characterized in that the processor is reset as soon as an abnormality is detected.