JPH023812A - System reset system - Google Patents

Abstract

PURPOSE:To reset a computer system in a state that information is not securely transferred by permitting a system controller to issue the inhibition request of using a common bus to a bus controller, and outputting a system reset signal after the bus is set to non-use. CONSTITUTION:When the system is reset, the system controller 100 issues the request that the using right of the common bus 300 is prevented from being newly issued to the bus controller 200. A means 5 inputting a signal showing that the common bus 300 is not used recognizes that the bus 300 is not used, and the reset of the system is controlled so that the system reset signal is outputted. Thus, the computer can be reset in the state that information is not securely transferred in the common bus.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a system control method for a computer system using a common bus method, and more particularly to a system reset method.

Conventional technology A conventional example will be explained with reference to FIG.

In a computer system using a conventional common bus method, when resetting the system, a request is made from the system panel 11' to the system control unit 12 to stop the central processing unit 13; , executes a command to the central processing unit 13 via the common bus to stop the operation of the central processing unit, and after the central processing unit 13 stops, and before the central processing unit 13 stops, input/output is executed for input/output processing. The controller 16 is instructed to input and output data between the input/output device and the storage device, and this is done at a time when the data transfer is completed.

A system reset request is made from the system panel 11' to the system control device 12, and the system control device 12
In accordance with this, the system outputs a reset signal via the common bus to devices connected to the common bus, thereby resetting the system.

Problems to be Solved by the Invention However, in the conventional system reset method described above, if the system reset is performed while data is being transferred from the input/output device in the input/output control device 16 to the storage device 14. Or, even if you intend to stop the central processing unit 13, due to a malfunction of the central processing unit 13, the central processing unit 13 will be deleted from the storage device! If a system reset is performed while data is being written to the storage device 14, the storage device 14 is removed from the system reset target and the memory contents are saved, but the storage device 14 remains on the common bus. When a system failure occurs, which is the main purpose of system reset, because the written data is not guaranteed, the system is stopped with the memory contents of the storage device 14 preserved, and the memory contents are restored. The disadvantage is that it becomes impossible to take measures to investigate the problem.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a new system reset method which makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, the system reset method according to the present invention uses a common bus method, and the common bus includes at least a central processing unit, a system control device, a bus control device,
A system reset signal is sent via the common bus to the system control device that performs various system controls in the computer system to which the storage device and input/output control device are connected, to reset the devices connected to the common bus. means for outputting a signal for requesting the bus control device to inhibit new granting of the right to use the common bus; and means for outputting a signal output from the bus control device to indicate that the common bus is not in use. It also has a means for inputting signals, and also has a predetermined priority order if it is in a state where bus usage requests made from multiple devices connected to the common bus are input and the right to use the common bus is newly granted. means for outputting a signal to the system control device indicating that the common bus is not in use to the bus control device that grants the right to use the common bus according to the system control device; and means for inhibiting the granting of a new right to use the common bus if the signal requesting to inhibit granting the right to use the common bus is in a state that requests to inhibit the right to use the common bus from being newly granted. and when a system reset is executed, the system control device requests the bus control device to inhibit new granting of the right to use the common bus, and inputs a signal indicating that the common bus is not in use; By controlling the system reset to output a system reset signal after recognizing that the common bus is not in use, it is possible to reset the computer system while information is not being transferred reliably on the common bus. It is possible to implement this.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Although the system control device generally has functions for controlling many systems in addition to those related to the present invention, a brief explanation of the drawings of portions that are not related to the present invention will be omitted. Furthermore, although the bus control device may also have functions other than the bus arbitration function, these portions that are not related to the present invention will be omitted.

Referring to FIG. 1, reference number 100 indicates a system control device, 200 indicates a bus control device, and 300 indicates a common bus.
In addition to the bus control device 200, a central processing unit, a storage device, an input/output control device, etc. (not shown) are connected, and a computer system is configured by these.

The memory circuit 3 stores microprograms for the system control device 100 to perform microprogram control, and the processor circuit 2 reads and executes the microprograms stored in the memory circuit 3 via the internal bus 11.

The system panel interface circuit 1 receives a request such as a system reset request from the system panel as a signal a, and when the request is read out from the processor circuit 2 via the internal bus 11, the system panel interface circuit 1 transmits data indicating the request contents to the processor circuit 2. Output for. When the bus arbitration suppression request circuit 6 receives a request to suppress bus arbitration from the processor circuit 2 via the internal bus 11, it sets the signal C to a state in which bus arbitration is suppressed, and when it receives a request to cancel the suppression of bus arbitration,
The signal C is set to a state in which bus arbitration is not inhibited. When the processor circuit 2 issues a read request via the internal bus 11, the bus arbitration state input circuit 5 outputs the state of the signal output from the bus control device 200 to the processor circuit 2. The signal S is a signal indicating whether the common bus 300 is in use or not, and the processor circuit 2 detects that the common bus 300 is not in use by inputting the state of this signal.

When the system reset signal output circuit 4 receives a system reset request from the processor circuit 2 via the internal bus 11, it outputs a reset signal to the devices connected to the common bus 300 as a signal.

When the bus arbitration circuit 10 of the bus control device 200 is in a state where the signal d indicates that the right to use the common bus is newly granted, the bus arbitration circuit 10 sends a bus use request signal e made from a plurality of devices connected to the common bus 300. Enter the common bus 30
If a bus use request is made from any device connected to 0, a signal f is sent to the device that has the highest priority right to use the bus according to a predetermined priority order.
Notifies that the right to use the common bus has been granted.

The bus arbitration circuit 10 notifies the bus timeout detection circuit 7 and the bus arbitration control circuit 8 by the signal g that the right to use the common bus 300 has been newly granted. When detecting that the right to use the common bus 300 has been newly granted based on the signal g output from the bus timeout, detection of a bus timeout is started. The bus timeout detection circuit 7 inputs a common bus control signal as a signal, monitors the end of bus use, and detects a bus timeout when the bus use is not completed within a predetermined time. 300 to forcibly terminate the use of the common bus 300. Also, the bus timeout signal i is the bus arbitration control port i? 88, and the bus arbitration control circuit 8 receives a signal g indicating that the right to use the common bus 300 has been newly granted.
Common bus 300 control signal j, bus timeout signal i
input, and outputs a signal indicating whether the common bus 300 is in use.

When the bus arbitration control circuit 8 detects that the right to use the common bus 300 has been newly granted based on the signal g, the bus arbitration control circuit 8 sets the signal g to a state indicating that the common bus 300 is in use.
When it is detected that the use of the common bus 300 has been terminated by the signal j, or when a bus timeout is detected by the signal i and the use of the common bus 300 is forcibly terminated, the signal 1 indicates that the common bus 300 is in use. The state indicates that it is not. The AND circuit outputs the state of the signal C as it is as the signal d when the signal C indicates a state in which new bus arbitration is not inhibited, and when the common bus 300 is in use, the bus arbitration circuit 10 Common bus 3
00j is detected as a state in which the right to use the history cannot be newly granted, and when the common bus is not in use, it is detected as a state in which the right to use the common bus 300 can be newly granted. Further, when the signal C indicates a state in which new bus arbitration is inhibited, the signal d is masked, and the same state as the state in which the common bus 300 is in use is output as the signal d, and the bus arbitration circuit 10 , it is detected that the right to use the common bus 300 cannot be newly granted. Next, the overall operation will be explained.

When the processor circuit 2 of the system control device 100 does not request the bus arbitration suppression request circuit 6 to suppress bus arbitration, that is, the state of the signal C is not masked by the signal C in the bus control bag f200. When the bus arbitration circuit 1O detects a state in which the right to use the common bus 300 is newly granted by the signal d, the bus arbitration circuit 10 outputs the common bus 300, which is input as the signal e, as it is.
00 is accepted, and if a bus use request is made, among the devices making the bus use request, the bus use right with priority a is given at this time. The bus timeout detection circuit 7 and bus arbitration control circuit 8 are notified by the signal g that the right to use the common bus 300 has been granted to the device having the common bus 300. If a bus use request has not been made, the acceptance of bus use requests continues until a bus use request is made, but during this time, the signal d is used to inhibit the granting of new rights to use the common bus 300. If detected, it stops accepting bus usage requests. When the bus timeout detection circuit 7 detects that the right to use the common bus 300 has been granted by the signal g, it monitors the end of the use of the common bus 300 by the signal g, and stops using the common bus 300 within a certain period of time. Monitoring ends when termination is detected. If the end of the use of the common bus 300 cannot be detected within a certain period of time, the signal i is used to forcibly end the use of the common bus 300, and a bus timeout occurs in the bus arbitration control circuit 8. to notify you of this. The bus arbitration control circuit 8 is
When it is detected that the right to use the common bus 300 has been newly granted by the signal g, the signal g is set to a state indicating that the common bus is in use, and while the common bus 300 is in use in the bus arbitration circuit 10, the common bus 300 is inhibited from being granted again. Thereafter, when the bus arbitration control circuit 8 detects that the use of the common bus 300 has been terminated by the signal j, or by the signal i,
When a bus timeout is notified, the signal S is set to a state indicating that the common bus 300 is not in use, and at this time, the signal S is not masked by the AND circuit, so it is output as is as two signals d, and the bus arbitration circuit 10 , a state in which the right to use the common bus 300 is newly granted is detected, and a request to use the common bus 300 made by the signal e is accepted.

During normal operation, the operations described above are performed in sequence, and arbitration of the common bus is performed.

When a system reset request is made from the system panel, the processor circuit 2 of the system control device 100 recognizes the system reset request from the system panel interface circuit 1 and implements control using a microprogram. In the control by the microprogram, first, a bus arbitration suppression request is made to the bus arbitration suppression request circuit 6, the signal C of the bus control device 200 is masked, and the bus arbitration circuit 10 controls the use of the common bus 300. The input is repeated from the zero-order bus arbitration state input circuit 5 until the common bus 300 is no longer in use, which is a state in which the granting of new rights is inhibited.

Thereafter, a request is made to the system reset signal output circuit 4 to output a reset signal. After the reset signal output state is canceled, the bus arbitration inhibition request circuit 7 is set to a state in which arbitration of the common bus 300 is not inhibited by the signal C. This completes the control operation by the microprogram.

As described in detail, according to the present invention, in a computer system using a common bus method, a system control device that performs various controls within the computer system is provided with a reset function for devices connected to the common bus. a means for outputting a system reset signal via the common bus to cause the bus control device to perform a system reset signal, a means for outputting a signal requesting the bus control device to refrain from newly granting the right to use the common bus, and a bus control device. means for inputting a signal indicating that the common bus is not in use, which is output from the common bus, inputs a bus use request made from a plurality of devices connected to the common bus, and newly acquires the right to use the common bus. means for outputting a signal to a system control device indicating that the common bus is not in use, to a bus control device that grants the right to use the common bus according to a predetermined priority if the common bus is in a given state; If the signal output from the control device that requests to suppress the granting of a new right to use the common bus is in a state that requests to suppress the granting of a new right to use the common bus, the common bus and means for inhibiting the granting of a new right to use the common bus, and when the system 11 is reset, the system control device issues a request to the bus control device to inhibit the granting of a new right to use the common bus. , after inhibiting the granting of a new right to use the common bus, it is recognized that the common bus is not in use by means of inputting a signal indicating that the common bus is not in use.
By controlling the system reset to output a system reset signal after the system reset, it is possible to reset the computer system without ensuring that information is transferred on the common bus. Since the contents of the storage device that is excluded from the target are reliably saved, it is easy to analyze the failure from the contents of the storage device when a system failure occurs, and information that will be valid in the event of a failure can be proactively left on the storage device. The effect is that the system can be constructed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram t151 showing one embodiment of the present invention, and FIG. 2 is a block diagram for explaining a conventional example. 110. System panel interface circuit, 211.
Processor circuit, 31. , memory circuit, 415. System reset signal output circuit, 511. Bus arbitration status input circuit, 669. Bus arbitration suppression request circuit, 73.7 Bus timeout detection circuit, 810. Bus arbitration control circuit, 9. ,,
AND circuit, 10. , , bus arbitration circuit, 11. ,. Internal bus, 100. ,, system control device, 200. ,
, bus control device, 300. ,,common bus

Claims (1)

[Claims] A common bus system is used to control the internal control of a computer system in which at least a central processing unit, a system control unit, a bus control unit, a storage device, and an input/output control unit are connected to the common bus. A means for outputting a system reset signal via the common bus to cause the system control device to perform the reset on devices connected to the common bus, and a means for newly granting the bus control device the right to use the common bus. a plurality of devices connected to the common bus, the device having means for outputting a signal for requesting to inhibit the transfer of data, and means for inputting a signal output from the bus control device indicating that the common bus is not in use; If a new bus usage request is input and the right to use the common bus is newly granted, the bus control device that grants the right to use the common bus according to a certain predetermined priority is notified that the common bus is not in use. means for outputting a signal indicating that the right to use the common bus is newly granted to the system control device; If the state requires that the right to use the common bus be inhibited, there is a means for inhibiting the granting of a new right to use the common bus, and when a system reset is performed, the system control device requests the bus control device to use the common bus. A system reset signal is output after recognizing that the common bus is not in use by making a request to suppress the granting of new usage rights and inputting a signal indicating that the common bus is not in use. A system reset method characterized by control.