JPH0831082B2 - System controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system using a common bus system, and more particularly to a system control device for controlling in a computer system.

[Conventional technology]

FIG. 3 shows an example of a computer system.

In this computer system, a central processing unit 12, a storage unit 13, a bus control unit 14 and a plurality of input / output control units 15 are connected to a common bus 11. In the central processing unit 12,
A system panel 16 for instructing an operation is connected, and an input / output device is connected to the input / output control device 15.

When the system is reset by this conventional device, the system panel 16 requests the central processing unit 12 to stop the execution of the instruction currently being executed. When the processing in the central processing unit 12 is stopped by this,
A system reset request is issued from the system panel 16 at a predetermined timing. Here, the predetermined timing means that the central processing unit 12 instructs the input / output control unit 15 to input / output data between an external device (not shown) and the storage unit 13 for input / output processing. The time around the end of the data transfer. When the system reset request is issued, the central processing unit 12 outputs a reset signal to the device connected to the common bus 11 via the common bus 11, thereby resetting the system.

[Problems to be solved by the invention]

By the way, in such a conventional system control device,
There is no guarantee that the data transfer between the external device and the storage device 13 has been completed when the central processing unit 12 outputs the reset signal. Therefore, if the system is reset while data is being written to the storage device 13, the storage device 13 itself is excluded from the target of the system reset, and the stored contents are taken into consideration. However, the data on the common bus 11 cannot be guaranteed. Therefore, the stored contents of the storage device 13 may be damaged. The main purpose of the system reset is to stop the system in a state where the contents of the storage device 13 are preserved when a system failure occurs and to investigate the failure from the stored contents. Therefore, if there is a possibility that a failure has occurred in the stored contents, there is a problem that the failure of the system cannot be investigated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a system controller capable of resetting the system while the common bus is surely stopped.

[Means for solving problems]

The present invention resides in (i) a computer system using a common bus system, which is connected to a common bus together with a central processing unit, a storage device, and an input / output control device, and which implements control in this computer system. If the control device is newly given the right to use the common bus, the device that has made the highest bus use request among the bus use requests output from a plurality of devices connected to the common bus A bus arbitration circuit that gives the right to use the common bus,
(Ii) The end of bus use is monitored after the right to use the common bus is given, and if the use of the bus does not end within a predetermined time, it is detected as a bus timeout and the bus is forcibly ended. A circuit, (iii) a bus arbitration control circuit for permitting or prohibiting the bus arbitration circuit from newly granting the right to use the common bus, and (iv) for causing a device connected to the common bus to perform a reset. A system reset signal output circuit that outputs a system reset signal via a common bus, and (v) prohibits new granting of the common bus usage right to the bus arbitration control circuit when performing a system reset, and a bus timeout detection circuit. The system reset signal output circuit to output the system reset signal after the time more than the time when the bus timeout is detected. A system control device is provided with a control circuit for controlling.

That is, in the present invention, after the bus use by the device to which the bus use right is given is terminated, or after the bus use is forcibly terminated by the bus timeout detection circuit,
The system reset signal is output so that the reset is performed while the data transfer on the common bus is completely stopped.

〔Example〕

 The present invention will be described in detail below with reference to examples.

FIG. 1 shows the configuration of a system controller according to an embodiment of the present invention.

The system control device 20 connects a system panel interface circuit 22, a processor circuit 23, a memory circuit 24, a bus arbitration circuit 25 and a system reset signal output circuit 26 to an internal bus 21.

Here, the memory circuit 24 stores microprograms for the system controller 20 to perform microprogram control. The processor circuit 23 is a memory circuit 24.
Is a circuit that reads out and executes the microprogram stored in (1) via the internal bus 21. The system panel interface circuit 22 is connected to a system panel (not shown) and receives a request from the system panel as a signal 31. When the processor circuit 23 issues an instruction to read the above-mentioned request via the internal bus 21, the data indicating the request content is output to the processor circuit 23.

The bus arbitration control circuit 25 uses the common bus via the internal bus 21.
When the request to prohibit the new grant of the usage right of 11 is received, it is supplied to the bus arbitration circuit 33 as the signal 32. The bus arbitration circuit 33 is a circuit that receives a bus use request sent from a plurality of devices connected to the common bus 11 as a signal 34 and performs arbitration. That is, the bus arbitration circuit 33 checks the signal 32 when the use of the bus is completed, and if the right to use the common bus 11 can be newly given, the bus use request having the highest priority is issued. A signal 35 is output to the device, indicating that the device has been granted the bus use right. Further, the bus arbitration circuit 33 inputs the control signal of the common bus 11 as a signal 36, and monitors the termination of bus use on the common bus 11.
The bus arbitration circuit 33 inhibits the grant of the bus use right when the signal 32 prohibits the new use right of the common bus 11.

The bus timeout detection circuit 37 inputs a signal 38 indicating that the bus arbitration circuit 33 has given the right to use the bus,
When the right to use the common bus 11 is given, the detection of the bus timeout is started. That is, the bus timeout detection circuit 37 sends the control signal of the common bus 11 to the signal.
Enter as 39 to monitor termination of use of common bus 11. Then, within a predetermined time, the common bus
If the use of 11 is not terminated, signal 41 is sent to the common bus.
Send to 11. As a result, the use of the common bus 11 is forcibly terminated.

The system reset signal output circuit 26 is a circuit that receives a system reset request from the internal bus 21 side and outputs a system reset signal as a signal 42 to the device connected to the common bus 11.

The operation of the system control device having the above configuration will be described below.

Normally, the bus arbitration control circuit 25 is set by the microprocessor executed by the processor circuit 23 to a state where the right to use the common bus 11 need not be given. In this state, the bus arbitration circuit 33 sequentially performs bus arbitration, and the bus timeout detection circuit 37 detects a bus timeout.

In this state, assume that a system reset request is issued from the system panel. The processor circuit 23 recognizes the system reset request by the output of the system panel interface circuit 22. Then, a series of control by the microprogram is performed. In this control, first, the bus arbitration control circuit 25 is requested to prohibit the new grant of the bus use right. In this way, the bus arbitration circuit 33 prohibits giving a new bus use right.

The processor circuit 23 requests the system reset signal output circuit 26 to output the system reset signal 42 after a lapse of time more than the time for detecting the bus timeout next. By thus waiting for a time longer than the time for detecting the bus timeout, the data transfer on the common bus 11 is completely stopped. That is, even if the bus is being used at the time when the new bus use right is prohibited, when the system reset signal 42 is output after the above time elapses, it depends on the device to which the bus use right is given. This is because either the use of the bus is terminated or the bus timeout detection circuit 37 forcibly terminates it.

After that, the processor circuit 23 sets the bus arbitration control circuit 25 in a state in which the bus usage right can be given. In this way, the microprogram control for the system reset request ends.

FIG. 2 shows a system configuration when the present invention is applied to a system equivalent to the conventional computer system shown in FIG. As shown in FIG.
The conventional bus controller 14 is the system controller 20.
It will be absorbed by. The system panel 16 connected to the central processing unit 12 is connected to the system controller 20.

〔The invention's effect〕

As described above, according to the present invention, when a system reset is executed, it is prohibited to newly give the right to use the common bus to the bus arbitration control circuit, and the bus timeout detection circuit detects the bus timeout for a time longer than the time. After a lapse of time, the system reset signal output circuit is controlled to output the system reset signal.
Therefore, the reset of the system can be easily realized with the common bus reliably stopped in one device. Also, since the contents of the storage device that are excluded from the system reset can be reliably saved, not only can the failure analysis be facilitated by the contents of the storage device when a system failure occurs, but also the failure occurrence. There is an effect that the system can be constructed so that the data that is sometimes effective is positively left in the storage device.

[Brief description of drawings]

FIG. 1 is a block diagram of a system controller according to an embodiment of the present invention, FIG. 2 is a block diagram of a computer system to which the system controller of this embodiment is applied, and FIG. 3 is a block diagram of a conventional computer system. is there. 11 …… Common bus, 20 …… System control device, 23 …… Processor circuit, 24 …… Memory circuit, 25 …… Bus arbitration control circuit, 26 …… System reset signal output circuit, 33 …… Bus arbitration circuit, 37 ...... Bus timeout detection circuit, 42 ...... System reset signal.

Claims (1)

[Claims] 1. A system control device in a computer system using a common bus system, which is connected to a common bus together with a central processing unit, a storage device, and an input / output control device, and which implements control in the computer system. If the new right to use the common bus is given to the common bus, the common bus is issued to the device which has the highest bus use request among the bus use requests output from the plurality of devices connected to the common bus. The bus arbitration circuit that gives the right to use the bus and the end of the bus use after the right to use the common bus is monitored, and if the bus use does not end within the prescribed time, the bus is timed out forcibly. A bus timeout detection circuit that terminates the use, and a bus arbitration control circuit that permits or prohibits the bus arbitration circuit to newly grant the right to use the common bus. And a system reset signal output circuit that outputs a system reset signal for causing a device connected to the common bus to perform a reset, and the use of the common bus for the bus arbitration control circuit when the system reset is performed. And a control circuit for controlling the system reset signal output circuit so as to output a system reset signal after a lapse of a time longer than the time at which the bus timeout detection circuit detects a bus timeout. A system control device comprising: