JPH01228028A - System control device - Google Patents

Abstract

PURPOSE:To control to output a system resetting signal after it is confirmed that a common bus is not used by confirming the condition of a signal to show that the use right of the common bus may be newly given. CONSTITUTION:When a bus arbitrating circuit 9 detects that the use right of a common bus 20 is newly given by a signal (d), a bus use request is received from respective devices connected to the bus 20. It is informed that the use right of the common bus 20 is given to the device having a priority bus use right by a signal (f) and the use right of the common bus 20 is given to a bus time out detecting circuit 4 and a bus arbitrating control circuit 6 by a signal (g). When it is detected by the circuit 4 that the use of the common bus 20 is not completed in the constant time, the use of the common bus 20 is forcibly assembled by a signal (i) and it is informed to the bus arbitrating control circuit 6 that the time-out occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to a computer system using a common bus system. The present invention relates to a system control device that performs control within a computer system.

〔overview〕

The present invention provides a system control device that controls a combinatorial system using a common bus, which removes a storage device from a system reset target when a system failure occurs, and
By reliably saving the memorized contents, it is possible to easily analyze failures from the contents of the storage device, and it is now possible to proactively leave data that will be valid in the event of a failure in the storage device. It is something.

[Conventional technology]

A conventional example will be explained with reference to FIG. In a computer system using a conventional common bus method, when resetting the system, the central processing unit 13 is sent from the system panel 11 to the system
In response, the system control device 12 executes a command to the central processing unit 13 to stop the operation of the central processing unit 13 via the common bus 20, and the central processing unit 13 stops. After that, central processing unit 1
3 stops, the data transfer in which the input/output control device 15 is instructed to input/output data between the input/output device (not shown) and the storage device 14 for input/output processing is completed. At this point, the system controller 11 requests the system controller 12 to reset the system.
In accordance with this, the system control device 12 outputs a reset signal to the devices connected to the common bus 20 via the common bus 20, thereby resetting the system.

[To the problem that the invention seeks to solve]

In the conventional system reset method described above, in the human output control device 15, data is transferred from an input/output device (not shown) to the storage device 14.
If a system reset is performed while data is being transferred to the device 1, or 1 has stopped the central processing unit 13, due to a malfunction the central processing unit 13 is transferring data to the device 1.
If data is being written to 4 and a system reset is performed during that time, the storage device 14 must be removed from the reset target and the contents must be saved to 1. Since the write data on the bus 20 is not guaranteed,
Note 1α of the device 14 when a system failure occurs
There is a drawback that it is not possible to stop the system while preserving the contents and investigate the failure from the stored contents.

The present invention solves these problems, and is designed to prevent storage devices from being damaged when a system failure occurs. It is an object of the present invention to provide a device that facilitates failure analysis based on α contents and that can leave data that will be valid when a failure occurs in a storage device.

Means for Solving Problem C] The present invention provides a system and a control device equipped with a means for sending a reset signal to a common bus according to a command from a system panel or a system panel. Means for prohibiting new bus arbitration of the common bus when a reset command is issued, and when a usage right is set for the common bus when a system reset command is issued from the system pile. The present invention is characterized by comprising means for prohibiting transmission of the system reset signal until the usage right is canceled.

In other words, in a computer system using a common bus method, the system control device that is connected to the common bus together with the central processing unit, storage device, and human output control device and performs control within the computer system is required to use the common bus. A means for detecting that the right to use the common bus can be newly granted and outputting a signal indicating that the right to use the common bus can be newly granted, and a processor controlling the system control device to grant the right to use the common bus. A means for making it possible to recognize the state of a signal indicating that the right to use the common bus may be newly granted, and a means for making it possible to recognize the state of a signal indicating that the right to use the common bus may be newly granted, based on a request from a processor controlling the system control device. If there is no request from the processor, a signal indicating that the right to use the common bus may be newly granted is output as is, and if a request is made from the processor, the right to use the common bus is output as is. masking means for forcibly masking a signal indicating that the right to use the common bus may be newly given, and outputting the signal as a state signal for inhibiting the granting of a new right to use the common bus, and a signal output from the masking means being common. If it is possible to newly grant the right to use the bus, in response to bus usage requests made from multiple devices connected to the common bus,
A bus arbitration means that grants the right to use the common bus according to a predetermined priority order, and a system reset signal that causes devices connected to the common bus to perform a reset based on a request from a processor that controls the system control device. and a system reset signal output means for outputting a system reset signal via the system, and when a system reset is performed, the mask means prevents the granting of a new right to use the common bus, and allows the right to use the common bus to be newly granted. The system reset is controlled so that the system reset signal is output after recognizing that the right to use the common bus is newly granted by the means that makes it possible to recognize the state of the signal indicated. That is.

[Effect]

By suppressing the granting of a new right to use the common bus when performing a system reset and making it possible to recognize the state of a signal indicating that the right to use the common bus may be newly granted, Control is performed to output a system reset signal after confirming that the common bus is not in use by confirming that the right to use the common bus is newly granted. This control makes it possible to reset the system in a state where it is certain that no information is being transferred on the common bus, and even in the event of a system failure, the storage device is removed from the system reset target and the storage Since the stored contents are reliably saved, it is easy to analyze failures based on the contents of the storage device, and data that will be valid when a failure occurs can be left in the storage device.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the system control device 12 according to the embodiment of the present invention, a system panel interface circuit 1, a processor circuit 2, and a storage circuit 3 connected to the system panel 11 shown in FIG. 2 are each connected to an internal bus 21. A system reset signal output circuit 10 is connected to the internal bus 21 and sends a system reset signal to the common bus 20 in accordance with a command from the system panel 11 shown in FIG. A bus arbitration suppression request circuit 7, an AND circuit 8, and a bus arbitration circuit 9 prohibit new bus arbitration of the common bus 20 when the system panel 11 issues a system reset command. The device includes a bus arbitration state input circuit 5 and a bus arbitration control circuit 6 which prohibit sending of a system reset signal until the usage right is released when set, and a bus timeout detection circuit 4 which detects bus timeout.

Although the system control device generally has functions for controlling many systems in addition to those related to the present invention, descriptions and descriptions of parts not particularly related to the present invention in the drawings will be omitted.

Next, each of the above-mentioned circuits will be explained below.

The memory circuit 3 stores microprograms for performing microprogram control. The processor circuit 2 reads out the microprogram stored in the memory circuit 3 via the internal bus 21 and executes it. The system panel interface circuit 1 receives a request such as a system reset request from the system panel 11 shown in FIG. is output to the processor circuit 2.

When the bus arbitration circuit 9 is in a state where the signal d indicates that the right to use the common bus 20 is newly granted, the bus arbitration circuit 9 inputs a bus use request signal e issued from a plurality of devices connected to the common bus 20, and When a bus use request is made from any device connected to the bus 20, a signal f is sent to the device having the highest priority right to use the bus according to a predetermined priority order to use the common bus 20. Notify that the right has been granted. It also notifies the bus timeout detection circuit 4 and the bus arbitration control circuit 6 by signal g that the right to use the common bus 20 has been newly granted.

When the bus timeout detection circuit 4 detects that the right to use the common bus 20 has been newly granted based on the signal g output from the bus arbitration circuit 9, it starts detecting a bus timeout. In addition, the common bus 200 control signal is input as a signal to monitor the termination of bus use, and if the bus use is not terminated within a predetermined time, a signal i is output to the common bus as a bus timeout. , common bus 20
Forcibly end the use of. Further, the bus timeout signal i is manually inputted by the bus arbitration control circuit 6.

The bus arbitration control circuit 6 inputs a signal g1 indicating that the right to use the common bus has been newly granted, a common bus control signal j, and a bus timeout signal i, indicating that the right to use the common bus has been newly granted. When it is detected that the right to use the common bus 20 has been newly granted by the signal g, the signal B is set to a state where the right to use the common bus 20 is inhibited from being newly granted, and the signal When it is detected that the use of the common bus 20 has been terminated, or when a bus timeout is detected in the bus timeout detection circuit 4 by the signal 1 and the use of the common bus 20 is forcibly terminated, the signal 1 is renewed. This state indicates that the right to use the common bus 20 is given to the user.

The bus arbitration state input circuit 5 outputs the state of a signal to the processor circuit 2 when a read request is made from the processor circuit 2 via the internal bus 21.

When the bus arbitration suppression request circuit 7 receives a bus arbitration suppression request from the pro sensor circuit 2 via the internal bus 21, the bus arbitration suppression request circuit 7 receives a signal C.
is set to a state in which bus arbitration is inhibited, and when a request to cancel the inhibition of bus arbitration is accepted, signal C is set to a state in which bus arbitration is not inhibited.

When the signal C is in a state where bus arbitration is not inhibited, the AND circuit 8 outputs the state of the signal S as is as the signal d, and when the signal C is in a state where bus arbitration is inhibited, the AND circuit 8 outputs the state of the signal d regardless of the state of the signal S. No. 8 is masked as a state in which newly granting the right to use the common bus 20 is inhibited. When the system reset signal output circuit 10 receives a system reset signal from the processor circuit 2 via the internal bus 21,
As a signal, a reset signal is output to devices connected to the common bus 20.

Next, the overall operation of the embodiment of the present invention will be explained. When the processor circuit 2 does not issue a bus arbitration suppression request to the bus arbitration suppression request circuit 7, that is, when the signal C
When the state of the signal S is not masked and is output as is as the signal d, when the bus arbitration circuit 9 detects a state in which the right to use the common bus 20 is newly granted based on the signal d, the state of the common bus 20 is newly granted using the signal e. It accepts bus use requests made from each device connected to the bus 20, and if a bus use request is made, the earliest bus use right among the devices making the bus use request is accepted. The bus timeout detection circuit 4 and the bus arbitration control circuit 6 are notified by the signal g that the right to use the common bus 20 has been granted to the device having the common bus 20.

If a bus use request has not been made, the acceptance of bus use requests will continue until a bus use request is made, but during this time, a condition is detected using signal d that inhibits the granting of a new right to use the common bus 20. If so, we will stop accepting requests to use the bus. When the bus timeout detection circuit 4 detects that the right to use the common bus 20 has been granted by the signal g, it monitors the end of the use of the common bus 2D by the signal g, and makes sure that the use of the common bus 20 is ended within a certain period of time. If detected, end monitoring. If the end of the use of the common bus 20 cannot be detected within a certain period of time, the use of the common bus 20 is forcibly terminated using the signal 1, and the bus arbitration control circuit 6
Notify that a bus timeout has occurred.

When the bus arbitration control circuit 6 detects that the right to use the common bus 20 has been newly granted by the signal g, the bus arbitration control circuit 6 sets the signal g to a state in which the right to use the common bus 20 is inhibited from being newly granted, and the bus arbitration circuit 9 To prevent the right to use a common bus 20 from being obtained again while the common bus 20 is being used. Thereafter, when the bus arbitration control circuit 6 detects by the signal J that the common bus 20 has been used for kJ[, or when the bus timeout is notified by the signal i,
The signal S is set to a state indicating that the right to use the common bus 20 is newly granted, and at this time, the signal S is not masked by the AND circuit 8, but is output as is from the AND circuit 8 as a signal d, and is outputted as is to the bus arbitration circuit 9. Notified that the right to use the bus 20 has been newly granted, the bus arbitration circuit 9 accepts a request to use the common bus 20. Normally, the operations described above are performed in sequence, and arbitration of the common bus 20 is performed.

When a system reset request is issued from the system panel 11, the processor circuit 2 recognizes the system reset request from the system panel interface circuit 1 and implements control by a microprogram. In the control by the microprogram, first, a bus arbitration suppression request is made to the bus arbitration suppression request circuit 7, the signal C is used to mask the signal d, and the signal d is used to suppress the new granting of the right to use the common bus 20. This prevents the bus arbitration circuit 9 from newly granting the right to use the common bus 20.

Next, input is repeated until the state of the signal S from the bus arbitration state input circuit 5 is detected indicating that the right to use the common bus 20 is newly granted. Thereafter, a request is made to the system reset signal output circuit 10 to output a reset signal. After outputting the reset signal, the bus arbitration suppression request circuit 7 is set to a state in which arbitration of the common bus 20 is not suppressed using the signal C, thereby terminating the control operation by the microprogram.

〔Effect of the invention〕

As explained above, according to the present invention, when a system failure occurs, a storage device is removed from the system reset target, and the failure is analyzed from the contents of the storage device in order to ensure that the stored contents are saved. Furthermore, there is an effect that data that will be valid when a failure occurs can be actively left in the storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional example. l...System panel interface circuit, 2...
Processor circuit, 3... Memory circuit, 4... Bus timeout detection circuit, 5... Bus arbitration state input circuit, 6
... Bus arbitration control circuit, 7... Bus arbitration suppression request circuit, ... AND circuit, 9... Bus arbitration circuit, 10.
... System reset signal output circuit, 11 ... System panel, 12 ... System control device, 13 ... Central processing unit, 14 ... Storage device, 15 ... Input/output control device, 20 ...・Common bus, 21...internal bus. 20 joints ≧ Boiled Fan 1 time

Claims (1)

[Claims] 1. In a system control device equipped with means (10) for sending a system reset signal to a common bus in accordance with a command from a system panel, when a system reset command is issued from the system panel, the above-mentioned Means for prohibiting new bus arbitration for the common bus (7, 8, 9), and if the right to use the common bus is set when a system reset command is issued from the system panel, the right to use the common bus is canceled. A system control device comprising means (5, 6) for prohibiting transmission of the system reset signal until the system reset signal is reset.