JPH0650038Y2 - DMA transfer protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a DMA transfer protection circuit, for example, to a protection circuit during data transfer in a DMA transfer mechanism of a microcomputer system.

[Prior Art] Conventionally, in a microcomputer system, a system down protection circuit for DMA data transfer, which is added to a DMA controller LSI, is often not used because a semiconductor product has high reliability.

In addition, even when using such a protection circuit,
The hardware timer only monitored the completion of all DMA transfer operations within a certain period of time.

FIG. 4 shows an example of such a conventional technique. In FIG. 4, the CPU 100 and the DMA controller (direct memory acc
ess controller) 102 is a data bus / address bus 10
4, the signal lines 106, 108 and 110 are connected to each other, and the system lock is input from the system clock generator 112.

The data bus / address bus 104 and the signal line 110 are
It is also connected to the memory 114.

Here, on the signal line 106, the hold request signal is DMA
The controller 102 outputs the signal to the CPU 100, the signal line 108 outputs a hold acknowledge signal from the CPU 100 to the DMA controller 102, and the signal line 110 exchanges a read / write signal.

Next, the operation of the above-mentioned conventional example will be described with reference to FIGS. Here, FIG. 5 shows a time chart in the case of data transfer of 1 byte.

First, when there is a DMA request in the DMA controller 102 (see SI in FIG. 6), a hold request (HRQ) signal is output from the DMA controller 102 to the CPU 100 via the signal line 106 (FIGS. 5A and 5B). ), See Fig. 6 S2).

Then, when this is input to the CPU 100 (see S3 in FIG. 6), the CPU 100 enters the hold state, and the hold acknowledge (HLDA) to the DMA controller 102 via the signal line 108.
A signal is output (see FIG. 5 (c) and FIG. 6 S4).

When this is input to the DMA controller 102 (see S6 in FIG. 6), an address enable (AFN) signal is output (see S6 in FIG. 5D), and then a read address is output (sixth in the sixth). Figure S7), read signal output (Figure 6 S8), write address output (Figure 6 S9), write signal output (Figure 6)
S10) is DMAed via address bus 104 and signal line 110
This is carried out from the controller 102 to the memory 111 (see FIGS. 5 (E) (F) (G)).

As a result, data reading or data writing is performed from the memory 114 via the data bus 104 (see FIG. 5 (H) and FIG. 6 S11).

Next, when the DMA ends, the hold request signal output from the DMA controller 102 is turned off (see FIG. 5 (B) and FIG. 6 S12).

On the other hand, in the DMA controller 102, the address enable signal is turned off (see FIG. 5 (D) and FIG. 6 S15).

As described above, in the conventional device, when a DMA request is made, the CPU 100 is first put in the hold state, then the data is read or written by the DMA, and then the hold state of the CPU 100 is released. ing.

[Problems to be solved by the device]

As described above, in the above-mentioned conventional technique, as shown in FIG. 5, a hardware timer is used to monitor the completion of all the operations of the DMA transfer for a fixed time.

Therefore, in the case where a dynamic RAM is used as the memory in the above-mentioned conventional technique, the memory contents have already been destroyed even if such a monitoring mechanism operates, so the state at the time of a DMA transfer failure is Not left. Therefore, there is an inconvenience that the cause of the defect cannot be specified.

[Purpose of device]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a DMA transfer protection circuit that can detect abnormal states in all processes in a DMA transfer in an extremely short time and can easily and reliably perform maintenance. , That is the purpose.

[Means for Solving the Problems]

In the present invention, in a DMA transfer protection circuit that is equipped in a system in which a memory is directly accessed by a DMA controller without going through a CPU to protect data transfer,
First monitoring means for monitoring the state of transfer of management right on the system bus between the controller and CPU, and second monitoring means for monitoring the state of read / write signals used at the time of reading / writing data from / to the memory And means.

Then, the first monitoring means has a management right transfer monitoring function for monitoring the transfer status of the management right of the system bus based on the DMA request signal output from the DMA controller and the response signal to the DMA request signal, and the management right of the system bus. And a first DMA controller stop control function which is activated when the transfer is not performed favorably and stops the operation of the DMA controller.

Further, the second monitoring means has a read / write signal monitoring function for monitoring the state of the read / write signal based on the address enable signal repeatedly output from the DMA controller, and the reading and writing of data are performed well. A second DMA controller stop control function is provided, which operates when there is no such operation, and stops the operation of the DMA controller. This aims to achieve the above-mentioned object.

[Action]

First, when a DMA request is generated in the DMA controller 12, a hold request signal is output to the CPU 10 and the DMA transfer protection circuit 11, respectively. When this is input to the CPU 10, the CPU 10 enters the hold state and the hold acknowledge signal is output to the DMA controller 12. Further, on the DMA transfer protection circuit 11 side, the management right monitoring counter 28 starts the counting operation by the hold request signal.

Next, the hold acknowledge signal output from the CPU 10 is input to the DMA controller 12 and the DMA transfer protection circuit 11, whereby the management right monitoring counter 28 is reset.

In the case of normal normal operation, the above operation is performed, and subsequently, the DMA transfer operation is executed.

On the other hand, when an abnormality occurs during the operation in which the management right of the system bus is transferred from the CPU 10 to the DMA controller 12, the following operation is performed.

That is, when the count operation of the management right monitoring counter 28 is continued in a state where the hold acknowledge signal is not output from the CPU 10, the DMA controller reset signal is sent from the management right monitoring counter 28 to the DMA controller 12 with a predetermined count amount.
Is output to the DMA controller, the DMA controller is initialized, and the operation ends.

As described above, if an error occurs when the management right is transferred at the start of DMA transfer, the operation is stopped before the start of data transfer.

Next, the data transfer operation after the transfer of the management right will be described.

First, the DMA controller 12 outputs an address enable signal to the R / W monitoring counter 32, and the R / W monitoring counter 32 starts counting operation.

Next, the read address output from the DMA controller 12
A read signal output, a write address output, and a write signal output are sequentially performed, and data reading and writing to the memory 22 are performed respectively.

In this case, when the read / write signal is input to the R / W monitor counter 32, the reset is performed. On the other hand, DMA
The controller 12 repeats the above operation,
Reading and writing of data by DMA is completed.

On the other hand, when an abnormality occurs during the above operation, the following operation is performed.

First, an abnormality occurs in reading and writing data to the memory 22, and the read / write signal is read by the R / W monitoring counter 32.
If it is not input to, the counter is not reset and the terminal is counted. As a result,
The operation end signal is sent from the R / W monitoring counter 32 to the DMA controller
It is output to 12, and the subsequent reading and writing of data is not performed. This prevents the data from being destroyed.

[Example of device]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3 (A).
A description will be given based on (B).

First, in FIG. 1, reference numeral 10 indicates a CPU as a main control unit for controlling the entire apparatus, and reference numeral 12 indicates a DMA controller. Between this CPU 10 and DMA controller 12, memory 22
And a DMA transfer protection circuit 11 is provided.

Of these, the DMA transfer protection circuit 11 does not need to go through the CPU 10.
The DMA controller 12 is provided in a system that directly accesses the memory 22 and has a function of protecting data transfer.

The DMA transfer protection circuit 11 includes a DMA controller 12 and a CPU 10.
A management right monitoring counter 28 as a first monitoring means for monitoring the transfer state of the management right related to the system bus between
An R / W monitoring counter 32 is provided as a second monitoring means for monitoring the state of a read / write signal used at the time of reading and writing data to the memory 22.

Then, the management right monitoring counter 28 is the DMA controller 12
Management right transfer monitoring function that monitors the transfer status of the system bus management right based on the DMA request signal output from the device and the response signal to it, and it operates when the transfer of the system bus management right is not performed well. Then DMA controller 12
The first DMA controller stop control function for controlling the stop of the operation.

Also, the second monitoring means has a read / write signal monitoring function for monitoring the state of the read / write signal based on the address enable signal repeatedly output from the DMA controller 12, and the reading and writing of data is performed well. It has a second DMA controller stop control function which operates to stop the operation of the DMA controller 12 when it does not exist.

More specifically, the CPU 10 and the DMA controller 12 are connected by lines 14, 16, 18 and 20.

Among these, the line 14 includes a data bus which is a bidirectional signal line for transmitting and receiving data, and an address bus which is a signal line for performing address designation in the memory. Is being exchanged.

Also, line 16 is the CP that normally manages the system bus.
A hold request signal requesting the abandonment of U10 is sent from the DMA controller 12, which is the CPU.
When input to 10, the CPU 10 enters the hold state, abandons the system bus, and outputs the hold acknowledge signal via the line 18.

Further, the line 20 is for transmitting / receiving a read / write signal which gives a read / write timing in the data transmitting / receiving operation.

Of these lines, line 14 and line 20 are memory
22 connected to each.

Next, a specific example of the DMA transfer protection circuit 11 will be described. This portion is surrounded by a broken line in FIG.

The lines 16 and 18 described above are each connected to the input side of an EXCLUSIV.OR (hereinafter referred to as "EX.OR") gate 24 forming a part of the DMA transfer protection circuit 11 on the one hand, and on the other hand.
EXCLUSIV NOR (hereinafter referred to as “EX / NOR”) gates 26 are respectively connected to the input side.

The output side of the EX / OR gate 24 is connected to the input side of the management right monitoring counter 28, and the output side of the EX / NOR gate 26 is connected to the input side of the AND gate 30 together with the line 20. There is. The output side of the AND gate 30 is also connected to the input side of the management right monitoring counter 28.

The CPU 10, the management right monitoring counter 28, and the R / W monitoring counter 32 are connected to the line by the system clock generator 34.
Clocks that are the basis of the system operation are input via 36.

Next, the output side of the management right monitoring counter 28 is connected to the DMA controller 12 by a line 38, and this and the R / W monitoring counter 32 are connected by lines 40 and 42, respectively.

Among these, the management right monitoring counter 28 outputs the request for acquisition of the system bus by the DMA controller 12, which causes the CPU 10 to relinquish the system bus and transfer the management right to the DMA controller 12. This is a counter that monitors the system bus until it is abandoned and the CPU 10 acquires the system bus again and obtains its management right.

From the management right monitoring counter 28, the DMA controller 12
A reset signal for initializing the signal is output via the line 38, and when this is input, the DMA controller 12 is in the initial state in any operating state.

The management right monitoring counter 28 as described above is the EX / OR gate 24.
Is used as a count enable signal and the output of the AND gate 30 as a reset signal. When the count value reaches a predetermined count value, the DMA controller reset signal is output and the DMA transfer operation is stopped. It is like this.

On the other hand, the R / W monitoring counter 32 is a counter that monitors the read / write signal during DMA transfer by the DMA controller 12, as described above.

The R / W monitor counter 32 has an address enable signal used for direction control of the system bus and enable control of a buffer for the address of the DMA controller output, etc.
It is adapted to be inputted from the DMA controller 12 via the line 40. An operation end signal for ending the DMA transfer operation of the DMA controller 12 is output from the R / W monitoring counter 32 via the DMA controller 42.

In this way, the R / W monitoring counter 32 is
It operates by using the address enable signal and the read / write signal that are input as the count enable signal and the reset signal as the reset signal, and when the predetermined count value is reached, the operation end signal is output to end the DMA transfer operation. There is.

Next, regarding the operation of the embodiment configured as described above,
A description will be given with reference to FIGS. 2 and 3.

Here, FIG. 2 shows a time chart of the operation in FIG. 1, and FIG. 3 shows its flowchart.

First, when a DMA request is generated in the DMA controller 12 (S100 in FIG. 3), the hold request signal is sent to the CPU1.
0 and the DMA transfer protection circuit 11 (see FIG. 2 (B) and FIG. 3 S101).

When this is input to the CPU 10 (see S102 in FIG. 3), the CPU 10 is in the hold state and the hold acknowledge signal is DMA.
It is output to the controller 12 (see FIG. 2 (C) and FIG. 3 S103).

On the other hand, on the DMA transfer protection circuit 11 side, since the hold request signal is input to the EX / OR gate 24 and the EX / NOR gate 26 respectively (see S104 in FIG. 3), their outputs are inverted ( See FIG. 2 (I) (J)). Also, AN
The output of the D gate 30 is also inverted (see FIG. 2 (K)).

Therefore, the management right monitoring counter 28 starts the counting operation together with the clock input (see FIG. 2 (A)) (see FIG. 2 (M) and FIG. 3 S103).

Next, the hold acknowledge signal output from the CPU 10 is input to the DMA controller 12 on one side (S106 in FIG. 3), and on the other side, the EX / OR gate 24 and the EX / NO.
Each is input to the R gate 26 (S107 in FIG. 3). Therefore, the outputs of these gates will be inverted,
(See FIGS. 2 (I) and 2 (J)), and the output of the AND gate 30 is also inverted (see FIG. 2 (K)). Therefore, the management right monitoring counter 28 is reset (see S in FIG. 2 (M) and FIG. 3).

In the case of normal normal operation, the above operation is performed, and subsequently, the DMA transfer operation is executed.

On the other hand, if an abnormality occurs during the operation of transferring the management right of the system bus from the CPU 10 to the DMA controller 12, the following operation is performed.

That is, if the count operation of the management right monitoring counter 28 is continued in the state where the hold acknowledge signal is not output from the CPU 10 (S110 in FIG. 3), the DMA controller reset signal indicates that the management right monitoring counter 2 has a predetermined amount of count.
Output from 8 to the DMA controller 12 (S1 in FIG. 3)
11). When this is input to the DMA controller (S112 in FIG. 3), the initialization is performed and the operation ends (S113, S114 in FIG. 3).

As described above, if an error occurs when the management right is transferred at the start of DMA transfer, the operation is stopped before the start of data transfer.

Next, the data transfer operation after the normal transfer of the management right will be described.

In this case, first, the DMA controller 12 or the address enable signal is output to the R / W monitoring counter 32 (see FIG. 2D and S115 in FIG. 3). When this signal is input, the R / W monitoring counter 32 starts counting operation (see S116A and S117A in FIGS. 2 (N) and 3).

Next, read address output (S116 in FIG. 3), read signal output (S117 in FIG. 3), write address output (S118 in FIG. 3), write signal output (FIG. 3) from the DMA controller 12.
S119) is sequentially performed (see FIGS. 2E, 2F and 2G), and data is read from and written into the memory 22 (see FIG. 2H).

In this case, when the read / write signal is input to the R / W monitor counter 32 (S120 in FIG. 3), the reset is performed (see FIG. 2 (N) and S121 in FIG. 3).

In the DMA controller 12, the above operation is repeatedly performed, and the DMA controller 12 reads data,
Writing is completed (see S122 in FIG. 3).

On the other hand, when an abnormality occurs during the above operation, the following operation is performed.

First, an abnormality occurs in reading and writing data to the memory 22, and the read / write signal is read by the R / W monitoring counter 32.
If it is not input to, the counter is not reset and the terminal is counted (S12 in FIG. 3).
3). As a result, the operation end signal is sent from the R / W monitoring counter 32.
It is output to the DMA controller 12 (S12 in FIG. 3).
4, S125) and subsequent data reading and writing will not be performed. This prevents the data from being destroyed.

Next, the operation of system management right transfer after data transfer will be described.

In this case, first, the hold request signal output from the DMA controller 12 is turned off (FIG. 2 (B), S126 in FIG. 3), and when this is transmitted to the CPU 10 (S127 in FIG. 3), the hold state is changed. It is released and the hold acknowledge signal is also turned off (Fig. 2 (e), 3rd).
(See Figure S128). This ends the operation of the CPU 10 in the DMA transfer (S130 in FIG. 3).

Further, in the DMA controller 12, the address enable signal is subsequently turned off (FIG. 2 (D), FIG. 3 S131),
The operation ends for the time being (S132 in FIG. 3).

On the other hand, on the DMA transfer protection circuit side, when the hold request signal is turned off (see S133 in FIG. 3), the EX / OR gates 24, EX
-The output of NOR gate 26 is inverted (Fig. 2 (I))
(See (J)), and the output of the AND gate 30 is also inverted (see FIG. 2 (K)).
Will be performed (see FIG. 2 (M) and FIG. 3 S134).

However, when the hold acknowledge signal is subsequently turned off (see S135 in FIG. 2 (c) and FIG. 3), the gates 24 and 26 are turned on.
And the outputs of 30 are inverted again (Fig. 2 (I) (J))
(See (K)) and the counter is reset (see (M) in FIG. 2 and S136 in FIG. 3), thereby ending the operation (step S137).

The above operation is performed when the transfer of the management right is normally performed, but when an abnormality occurs, the operation is as follows.

First, if neither the hold request signal nor the address enable signal is turned off (S133, S138 in FIG. 3).
(See S) of FIG. 3, the R / W monitoring counter 32 performs a counting operation (S117 in FIG. 3), assuming that an abnormality has occurred in reading and writing of data.

Next, when the hold acknowledge signal is not turned off, the management right monitoring counter 28 continues counting, and when the terminal counting is performed (S129 in FIG. 3), a reset signal is output to the DMA controller 12. This is the case (Fig. 3, S140). When this is input (Fig. 3, S1
41), the DMA controller 12 is initialized (S142 in FIG. 3), and the operation ends (S14 in FIG. 3).
3).

As described above, according to this embodiment, since the DMA transfer operation start / end process and the DMA transfer in progress are monitored by different counters, respectively, the memory destruction of the dynamic RAM does not occur. In a very short time, it is possible to satisfactorily detect abnormal conditions related to all processes related to DMA data transfer.

Therefore, for example, by latching the required signal when an abnormal condition is detected and performing appropriate processing, it is possible to specify the location of the defective condition of the hardware and display it, facilitating maintenance work. Is possible.

It should be noted that the present invention is not limited to the above-described embodiment at all, and the circuit configuration can be changed so that, for example, the same operation is achieved.

[Effect of device]

Since the present invention is configured and functions as described above, according to this, the first monitoring means is configured to transfer the management right of the system bus based on the DMA request signal output from the DMA controller and the response signal to the DMA request signal. Since it is configured to monitor the start / end process of the DMA transfer operation, that is, the transfer state of the management right of the system bus, the second monitoring means is repeatedly output from the DMA controller. Read based on address enable signal
Since it is configured to monitor the state of the write signal, it is possible to constantly monitor the write / read status of the data during the DMA transfer, so that the DMA data can be monitored in an extremely short time without memory corruption. It is possible to satisfactorily detect abnormal conditions related to all processes related to transfer, and when any of the monitoring means detects an error, the operation of the DMA controller is controlled to stop, so that the data in the memory can be reliably stored. In addition, by latching the information obtained by each of the above-mentioned monitoring means and storing it in a predetermined memory, it is possible to immediately and surely display the status of the hardware failure and its defective location. Therefore, it is possible to reduce the trouble of finding a defective portion each time maintenance is performed, and improve the efficiency of maintenance work. Practical DMA unprecedented say
A transfer protection circuit can be provided.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG.
FIGS. 3A to 3N are time charts showing the operation of the embodiment in FIG. 1, FIGS. 3A and 3B are flow charts showing the operation of the embodiment in FIG. 1, and FIG. 5 is a time chart showing the operation of the conventional example, and FIG. 6 is a flow chart showing the operation of the conventional example. 10 …… CPU, 12 …… DMA controller, 22 …… Memory, 28
...... A management right monitoring counter as the first management right monitoring means, 32 ...... A R / W monitoring counter as the second management right monitoring means.

Claims (1)

[Scope of utility model registration request] 1. A DMA transfer protection circuit, which is provided in a system for directly accessing a memory by a DMA controller without passing through a CPU and protects data transfer, comprising a management right for a system bus between the DMA controller and the CPU. A first monitoring means for monitoring the transition state of
Second monitoring means for monitoring the state of a read / write signal used at the time of reading and writing data to and from the memory is provided, and the first monitoring means is provided with a DMA request signal output from the DMA controller. A management right transfer monitoring function for monitoring the transfer status of the management right of the system bus based on a response signal to the DMA controller, and operates when the transfer of the management right of the system bus is not performed well to the DMA controller. A second DMA controller stop control function for stopping and controlling the operation, wherein the second monitoring means monitors the state of the read / write signal based on an address enable signal repeatedly output from the DMA controller. The read / write signal monitoring function operates when the data is not read or written well, and the DMA controller operates. DMA transfer protection circuit characterized in that it comprises a first 2 DMA controller stop control function for stopping controlling the operation to controller.