JPS63200254A - Memory write control circuit - Google Patents

Abstract

PURPOSE:To avoid the miswrite of data to a RAM by allowing the write of data to the RAM only for a prescribed period of time from a time point when the specific data is written into a specific address. CONSTITUTION:A CPU 1 is connected to a RAM 5 via buses 2 and 3. A decoding circuit 6 connected to both buses 2 and 3 detects the specific data written into a specific address in the circuit 6 and delivers a pulse. This pulse starts a timer 7 and the output of this timer 7 is applied to a write terminal of the RAM 5 via an OR gate circuit 8. Thus the write of data is possible to the RAM 5 before the timer 7 has a time-up state. Thereafter no data is written into the RAM 5.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to R A in microcomputer systems.
M (Random Access Memory)
This invention relates to a write control circuit.

[Conventional technology]

Generally, when writing data to the RAM provided in a microcomputer system, a write signal from the CPU is output to the RAM write terminal, but in conventional microcomputer systems, the RAM write terminal is It is directly connected to the CPU0 write terminal using a write signal line, etc., and the CPU
Writing to the RAM is possible whenever a write signal is output from the write terminal of the RAM.

[Problem that the invention seeks to solve]

In the conventional microcomputer system described above, since it is possible to write to RAM at all times, for example, if a program error or program runaway occurs and the RAM is erroneously written, then when the system is reset and restarted, , there is a risk that important data in the RAM will be destroyed.

When a program runs out of control, it is possible to automatically restart the program using, for example, an automatic normal reset, but there is no means to prevent data destruction.

An object of the present invention is to provide a memory write control circuit that can prevent erroneous writing to RAM and reliably prevent data destruction in RAM.

[Means for solving problems]

The memory write control circuit of the present invention includes a decoder circuit that detects and outputs specific data written to a specific address, and a timer that is activated by the output of this decoder circuit and holds the output until time-up. and R from the CPU
The write signal output to AM is controlled based on the output signal of the timer, and the write signal is R only during the timer time-up.
It is equipped with a gate circuit configured to be able to output to AM, and prohibits writing to RAM except during this period to prevent R in the event of a runaway.
It is configured to prevent erroneous writing to AM and data destruction.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention in blocks. The CPUI has an address terminal Addr and a data terminal Data connected to an address bus 2 and a data bus 3, respectively, and a RAM 5 is connected through these buses 2.3. In addition, a decoder circuit 6 is connected to the bus 2°3.
is connected, and this decoding circuit 6 is connected to the CPUI.
The decoder circuit is connected to the write terminal (2) by a write signal line 4, and is configured to detect when specific data is written to a specific address in the decoder circuit and output a pulse. A timer 7 is connected to the output end of the decoder circuit 6, which is activated when a signal from the decoder circuit 6 is input, and can hold the output until a predetermined time elapses (time-up). Furthermore, the output of this timer 7 is connected to one input of an OR gate circuit 8. The write signal line 4 is connected to the other input of the OR gate circuit 8, and the output of the OR gate circuit 8 is connected to the write terminal (2) of the RAM 5.

Next, a write operation using the above circuit configuration will be explained.

FIG. 2 is a timing diagram for explaining the operation of the circuit of FIG. 1. In the figure, Addr is address bus 2
．． [1ata is the data bus 3, 1cPtl is the write signal of the CPU 1, and Timer out is the output of the timer 7.

(2) RAM shows each output waveform of the gate circuit 8.

In the same figure, first, at tl, when specific data D is written to specific address A8 of the decoder circuit 6 by the CPUI, the timer 7 is started by the decoder circuit 6, and Timer 7 is started by the decoder circuit 6.
er out becomes “L”. This state is RAM write permission.

Next, assume that the CPUI writes data to the RAM 5 at t2. That is, when the RAM address ARAM is set on the address bus 2, the data D2 to be written is set on the data bus 3, and the write signal ■CPu is set to "L",
Both inputs of the gate circuit 8 become "Yes", and the output, that is, R
The signal 1ifRRAM applied to the write terminal basket of AM5 also becomes "Ll", and the data on the data bus 3 is written into the RAM5.

When the time-up time T of timer 7 has elapsed (t3)
, the output of timer 7 becomes "H". After that, if t
Even if the data D4 is written to address AII in the RAM 5 in step 4, the output of the gate circuit 8 remains at "H" and no data is written to the RAM 5. To perform writing, the specific data Dx is written again to the specific address A of the decoder circuit 6, and writing to the RAM 5 is possible for a period of T from that point.

Therefore, in this example, writing to the RAM is possible only for a certain period of time T from the time when the specific data D8 is written to the specific address A8 of the decoder circuit 6, so even if the CPU goes out of control, the data in the RAM is The risk of writing erroneous data to an address is extremely reduced, erroneous writing to RAM can be prevented, and data destruction etc. can be reliably prevented.

〔Effect of the invention〕

As explained above, in the present invention, a decoder circuit detects that specific data has been written to a specific address, the output activates a timer, and the data is transferred from the CPU to the RAM only until the timer times up. Since it is configured to be able to output a write signal, it is possible to write to the RAM only for a predetermined period of time from the time when specific data is written to a specific address. The probability of writing specific data to an address becomes extremely small, and erroneous writing to the RAM can be prevented and data destruction etc. can be reliably prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the circuit shown in FIG. 1...CPU, 2...Address bus, 3...Data bus, 4...Write signal line, 5...RAM, 6...
...Decoder circuit, 7...Timer, 8...OR gate circuit. Figure 1 Figure 2

Claims (1)

[Claims] (1) In a microcomputer system equipped with a CPU and RAM, there is a decoder circuit that detects that specific data has been written to a specific address and outputs it, and the decoder circuit is activated by the output of this decoder circuit and outputs the output until time is up. a timer that maintains the , and a write signal outputted from the CPU to the RAM based on the output signal of the timer;
A memory write control circuit comprising: a gate circuit configured to be able to output a write signal to the RAM only during the time-up period.