JPH0535537A - Data transfer controller - Google Patents

Abstract

PURPOSE:To detect the abnormality and the fault of a transfer address while the date are transferred between an input/output device and a main storage. CONSTITUTION:A control part block 90 that received an operation instruction fetches the transferred data from an input/output device 200. When the data transferred from the device 200 are fetched by a data path part block 70, a control part 90 sends the address held by a memory address counter 54 to a main storage 300 through a memory bus 10. At the same time, a comparator 51 compares this address with the range registers 52 and 53. The counter 54 is counted up with each transfer of a single unit. Meanwhile a transfer word number counter 55 is continuously counted down until the value of the counter 55 is set at O. When both registers 52 and 53 detect the deviation from the range of a transfer address in a series of transfer operations, this fact is reported to the outside with a fault detection signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device for controlling data transfer between a main memory device and an external input / output device, and more particularly to a data transfer control device for detecting a failure of a transfer address.

[0002]

2. Description of the Related Art Generally, in a data transfer control device for transferring data between a main memory device and an input / output device, an address for data transfer is supplied to the main memory device when accessing in the main memory device. .

In a conventional data transfer control device, a memory address counter and a transfer word number counter are set by a control microprocessor (MPU) block before data transfer, and then a start instruction is given to the control block. Thus, the transfer operation is started. When the transfer is started, the memory address counter counts up by one unit each time the main memory is accessed, and the transfer word number counter counts down by one unit. This transfer operation is repeated until the transfer word number counter becomes 0 (zero) or a failure is detected.

[0004]

However, in the above-mentioned conventional data transfer control device, a transfer address system failure, for example, a count-up failure of the memory address counter, a send memory address destruction, or a transfer word number. A countdown failure of the counter or the like occurs, and a failure that cannot be detected in the parity check of the memory address causes an access outside the regular data area, which causes the destruction of the program or the data. If this kind of failure is not detected instantly, the failure becomes latent because the logical depth is deep, and if a considerable time has not passed, the abnormality cannot be detected, and furthermore, it is difficult to detect the failure site. The problem is that it takes a long time to recover from a disaster.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a data transfer control device capable of detecting an abnormal transfer address in a short time.

[0006]

In order to achieve the above object, a data transfer control device of the present invention has a data transfer control device for transferring data between an input / output device and a main storage device. Two kinds of range register circuits for the lower limit and the upper limit to be monitored, comparing means for comparing and confirming that the memory address being transferred is between the two kinds of range registers, and the comparing means deviates from the range. And a failure detection signal sending means for sending a failure detection signal immediately when the is detected.

Further, in the data transfer control device for fetching the transfer data between the input / output bus of the input / output device and the memory bus of the main storage device by the data path block and transferring between the buses, the transfer data is transferred for each unit. , A memory address counter circuit for transmitting a transfer address prior to the above and performing a count-up operation for one unit thereafter, a transfer word number counter circuit for performing a count-down operation for one unit of the transfer word number for each transfer of one unit, and a data transfer A first range register circuit that holds a lower limit address of an area, a second range register circuit that holds an upper limit address of a data transfer area, and a memory address transmitted from the memory address counter circuit are monitored on a memory bus. Means and two types of memory devices held in the first and second range register circuits. Means for reading a response, comparing means for comparing the monitored memory address on the memory bus with the range specified by the two types of range registers, and when the comparing means detects a range deviation of the memory address, And a fault signal transmitting means for activating the fault signal and transmitting the fault signal to the outside.

Further, if necessary, the transmission of the transfer data subsequent to the transmission of the transfer address is stopped when the fault signal is transmitted from the fault signal transmitting means.

[0009]

According to the data transfer control device having the above configuration, whether or not the memory address being transferred is between two types of range registers is compared for each unit of transfer, and if the range is exceeded, a failure occurs. The detection signal is sent out and is used for, for example, stopping the transfer operation.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, a data transfer control device 100 is a memory bus (MEM BUS) 1 of an external main storage device 300.
0, input / output bus of input / output device 200 (IO BUS) 3
0, the internal local bus 20, the comparator 51, the range register U holding the upper limit address of the data transfer area
52, a range register L53 for holding the lower limit address of the data transfer area, a memory address counter 54, a transfer word number counter 55, a data path block 70, an MPU block 80 and a control block 90.

The memory address counter 54 transmits the transfer address preceding the transfer data for each unit, and thereafter performs a count-up operation for one unit. Further, the transfer word number counter 55 counts down the transfer word number by one unit for each transfer of one unit. The comparator 51 has a function of monitoring the memory address transmitted from the memory address counter 54 on the memory bus and a function of reading out two types of memory addresses held in the first and second range registers 52 and 53. When,
A comparison function that compares the memory address monitored on the memory bus with the range specified by the two types of range registers 52 and 53, and when a range deviation of the memory address is detected, activates a fault signal to the outside. And a fault signal transmitting function for transmitting.

Further, ahead of the comparator 51, there is provided a stop circuit (not shown) for stopping the transmission of the transfer data following the transmission of the transfer address when the fault signal is transmitted.

The data transfer control device 100 controls the transfer between the main storage device 300 and the input / output device 200. Prior to this, the internal MPU block 80 stores the transfer destination address to the main storage device 300 in the memory. The address counter 54 is set, and the transfer word number is set in the transfer word number counter 55. Further, the lower limit memory address and the upper limit memory address of the transfer destination data area of the main memory are set in the range register L53 and the range register U54, respectively. After that, the MPU block 80 instructs the control block 90 to start the transfer operation.

Next, from the input / output device 200 to the main storage device 3
The transfer operation to 00 will be described. Upon receiving the operation instruction, the control block 90 goes to the input / output device 200 for the transfer data. The transfer data from the input / output device 200 is
When loaded in the data path block 70, the control unit 9
0 stores the memory address held in the memory address counter 54 on the memory bus 10 and
To 00. At this time, the comparator 51 monitors the memory bus 10 and confirms that the transfer address is within the area designated by the range register L53 and the range register U54. After confirmation, the control unit block 90 takes out the transfer data from the input / output device 200 held in the data path unit block 70, puts it on the memory bus 10, and transfers it to the main storage device 300 for one unit. .

For each transfer of one unit, the memory address counter 54 counts up by one unit, and the transfer word number counter 55 counts down by one unit to prepare for the next transfer operation. This series of operations is
The countdown value of the transfer word number counter 55 is "0".
Repeat until it reaches (zero). During this series of transfer operations, the comparator 51 is performing a range inspection of the transfer address,
When the deviation of the transfer address caused by a failure is detected, the failure detection signal 60 is immediately activated to report it to the outside, and the control block 90 terminates the operation of transmitting the transfer data following the transfer address. By this operation, data destruction of the main memory device 300 can be prevented.

[0017]

As described above, the data transfer control device of the present invention monitors the transfer address sent to the memory bus for each transfer of one unit, and uses one comparator and two range registers. By using this, the range of the data area is inspected, so that the transfer address abnormality can be detected in a short time. Therefore, recovery from a failure can be greatly shortened, and data destruction of the main memory device is prevented in advance, which has the effect of improving reliability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer address control device according to an embodiment of the present invention.

[Explanation of symbols]

10 Memory Bus (MEM BUS) 20 internal bus 30 Input / Output Bus (IO BUSU) 51 comparator 52 Range register U 53 Range register L 54 memory address counter 55 Transfer word counter 60 Fault detection signal 70 Data path block 80 MPU block 90 Control block 100 data transfer control device 200 I / O equipment 300 main memory

Claims (3)

[Claims] 1. A data transfer control device for transferring data between an input / output device and a main memory device, comprising two types of range register circuits for monitoring a data area of the main memory device, a lower limit and an upper limit, and a memory being transferred. Comparing means for comparing and confirming that the address is between the two types of range registers for each unit of transfer; and fault detecting signal transmitting means for immediately transmitting a fault detecting signal when the comparing means detects a range deviation. A data transfer control device comprising: 2. A data transfer control device for fetching transfer data between an input / output bus of an input / output device and a memory bus of a main memory device by a data path block and transferring between the buses, transfer data for each unit. , A memory address counter circuit for transmitting a transfer address prior to the above and performing a count-up operation for one unit thereafter, a transfer word number counter circuit for performing a count-down operation for one unit of the transfer word number for each transfer of one unit, and a data transfer A first range register circuit that holds a lower limit address of an area, a second range register circuit that holds an upper limit address of a data transfer area, and a memory address transmitted from the memory address counter circuit are monitored on a memory bus. Means and two types of memory addresses held in the first and second range register circuits Means for reading out, a comparing means for comparing the monitored memory address on the memory bus with a range specified by the two types of range registers, and a failure when the comparing means detects a deviation of the range of the memory address. A data transfer control device comprising: a fault signal transmitting means for activating a signal and transmitting the signal to the outside. 3. The data transfer according to claim 1, further comprising stop means for stopping transmission of transfer data subsequent to transmission of the transfer address when the failure signal is transmitted from the failure signal transmitting means. Control device.