JPS5831552A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5831552A
JPS5831552A JP12952181A JP12952181A JPS5831552A JP S5831552 A JPS5831552 A JP S5831552A JP 12952181 A JP12952181 A JP 12952181A JP 12952181 A JP12952181 A JP 12952181A JP S5831552 A JPS5831552 A JP S5831552A
Authority
JP
Japan
Prior art keywords
film
window
sio2
semiconductor device
sio2 film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12952181A
Other languages
Japanese (ja)
Other versions
JPH0420266B2 (en
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12952181A priority Critical patent/JPS5831552A/en
Publication of JPS5831552A publication Critical patent/JPS5831552A/en
Publication of JPH0420266B2 publication Critical patent/JPH0420266B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Abstract

PURPOSE:To provide a high speed and complete dielectric isolation semiconductor device and a manufacturing method of the device by forming an SiO2 film partly opened with a window on the surface of an Si substrate, a single crystal Si film on the window and burying the window as a dielectric isolation SiO2 by a thermal oxidation in contact with a primary SiO2 film. CONSTITUTION:An Si film is formed by a CVD method by a thermal isolation of an SiH4 on the overall surface of the substrate. A polycrystalline Si film is formed on both the window and the SiO2 film when the CVD method is performed at a relatively low temperature. An Si films is melted by a lamp, an Si3N4 film is removed by photoetching on the primary window, the Si film is thermally oxidized, and a dielectric isolation SiO2 film 8 is formed. After a P type well 9 and an N type well 10 are formed, a gate SiO2 film 11, a gate polycrystalline Si electrode 12 and a source and drain region 13 is formed by an impurity diffusion, and a CVD SiO2 film 14 and an aluminum electrode wire 15 are then attached to complete a semiconductor device.

Description

【発明の詳細な説明】 本発明に半導体装置とその製Ｉ方法に係り、とりわ＃ｒ
ｊ鋳電体分峨牟導体装置とその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same.
J. This invention relates to a cast electric body conductor device and its manufacturing method.

従来、誘電体分離半導体装ＩＩ！Ｉと丈の製造方法の代
表的なものとして、５Ｏ８（シリコン・オン・サファイ
ヤ）によるサファイヤ絶縁基板１：の単結晶８１Ｍ’ｔ
−用いた完全誘電体分離半導Ｉ４装置が、を】る。Conventionally, dielectric isolation semiconductor device II! As a typical manufacturing method for I and length, a single crystal 81M't of sapphire insulating substrate 1 made of 5O8 (silicon on sapphire) is used.
- The fully dielectrically isolated semiconductor I4 device used is

しかし、従来のｄＯＢＫよる誘晰体分離半導体装置では
サファイヤ基板が？Ｌ４１曲であり、一般Ｊ４−１に向
かないという欠点がある。However, in the conventional dOBK lucid separation semiconductor device, is the sapphire substrate used? It has the disadvantage that it is an L41 song and is not suitable for general J4-1.

さらに、従来の８１基板上への半４悸装置ｍ　−Ｃぼ＃
Ｓ電体分離かできす、高速性能に限界を生じるという欠
点があった。In addition, the semi-four-wheel drive device m-C on the conventional 81 board
This had the drawback of having to separate the S-electrode, which placed a limit on high-speed performance.

本発明に、かかる従来技術の欠Ａｋなくシ、実測で高速
な完全８電体分離牛導体装、にとその装造方法を礎共す
ることｔ目的とする。It is an object of the present invention to eliminate the deficiencies of the prior art and to provide a complete 8-electrode isolated conductor system that is actually high-speed and provides a method for its construction.

上記目的に達成するための本発明の基本的な横ｂｙ、は
、８１基根表面に４部分的に窓開けばれ罠Ｓ１０．膜が
形成され、該窓部およ（ｐ、；ｉｏ、楼土しくａ申結晶
Ｓ１膜が形成され、前舵窓部上しン単結晶Ｓ１膜６熱酸
化により誘電体分ｗ＃８１（ｈとして、前記下地Ｓｉ　
ＯＨＩＮけ接して、前記窓部ｒ埋め込んで形成さ才ｔ１
いる場を物像と−する。The basic aspect of the present invention to achieve the above object is to have four partially fenestrated traps S10. A single crystal S1 film is formed on the window and (p,; h, the base Si
The window portion R is formed by embedding the window portion R in contact with the OHIN.
Consider the place you are in as an object image.

以下、実施ｙｌ＋に沿って本発明を旺述−ｒつ。Hereinafter, the present invention will be described in detail along with the implementation.

第１１凶（ａ）〜（ｇ）に本発明による妨ボ陣号講〇−
ＭＯＢ　　ＩＣ倉製造工程１威に縦万同障ｆ圓図と（、
て／■ζしｋものである。No. 11 (a) to (g) are the sabojingoko according to the present invention 〇-
MOB IC warehouse manufacturing process 1 with vertical mandou f round diagram (,
te/■ζshik thing.

８１基板ｉ上に形成し友薄い８１０．祠２とその上Ｖ（
−ＣＶＤｄｌｌｌよる８１ｍＮ＊Ｍ１　ｓ　を形成し、
ホト（Ｐ、Ｒ）・エツチングに工９窓都となる部分のｄ
ｉｓＮ、膜を残してＳｉ、Ｎ、喚を除去し、該残存８ｉ
１Ｎ４膜を酸化マスクとして、熱酸化Ｖ（エリ−３１０
２膜４を厚く形成する。次いで、ＳｉＨ，の熱分循ＶＣ
よるＣＶＤ法よりＳ１膜５ｔ−基板全回に形ｔＳ、−す
るのであるが、９００℃〜１２００℃の萬搗でＣνＤｔ
行なう場ＭＫｔｊ窓部上の８１躾は単結晶ｄ１膜となり
、ｓｉｏ、Ｍｉ４上の８１膜は多結晶５ｉＩ−となるが
、５００℃〜８００℃の比較的低重で０１／Ｄｔ行なう
と窓部上も５１０ｇ膜上もいずれも多結晶８１ｍとなる
。この嚇自は績♂ピの方法による例を示した。次に表面
からＢ１膜５ヶランプにより−ＰＩ４　Ｌ事納晶化ｄｌ
い酸化ｙＪ６とｑＶＤによる”Ｌｓｋ４＋４７を形成し
、ホト・エツチングにエリ大地窓部上の１：＋１ｘＮ４
１１１１を除去し、該Ｓｉ、Ｎ、膜７を酸化マスクとし
てＳ　ｉ　Ｍ　５　ｔ−熱酸化すΣことにより窓部を埋
めｆｃｌｆ！電体分−８１０，８’ｌ形成する。以鏝に
通虜のＣ−ＭＯＳ　　工Ｃの製造方法にのっとり、Ｐウ
ェル９とＮウェル１０の′１域を形成後、ケー）１３１
０．膜１１、ゲート多結晶Ｂ１電極盲２、不純切拡赦に
よるソース・ドレイン領域１３寺を形成後、ＯＶ　Ｄ−
ＵｉＯｌ　ｐ　１４、成電爾配ｄｉ　ｔ　５　ｆ形成し
て完成する。81 formed on the substrate i and thin 810. Shrine 2 and above V (
- form 81 mN*M1 s by CVDdlll,
d of the part that becomes the 9th window capital in photo (P, R) etching
isN, Si, N, and carbon are removed leaving the film, and the remaining 8i
Using the 1N4 film as an oxidation mask, thermal oxidation V (Elli-310
2. The film 4 is formed thickly. Then, the heat distribution VC of SiH,
By the CVD method according to
When performing 01/Dt on the MKtj window part, it becomes a single crystal d1 film, and the 81 film on sio, Mi4 becomes a polycrystalline 5iI- film, but when performing 01/Dt at a relatively low gravity of 500°C to 800°C, the window part Both the top and the 510g film are polycrystalline 81m. This threat showed an example using the method of the student pi. Next, from the surface with 5 lamps of B1 film - PI4 L crystallization dl
Form "Lsk4+47" by oxidizing yJ6 and qVD, and photo-etching 1:+1xN4 on the edge ground window.
1111 is removed, and the window portion is filled by performing Si M 5 t-thermal oxidation using the Si, N, and film 7 as an oxidation mask, and fclf! An electric component of -810,8'l is formed. After forming the '1 area of the P well 9 and the N well 10 according to the manufacturing method of C-MOS technology C, which was developed by an expert, C) 131
0. After forming the film 11, gate polycrystalline B1 electrode blind 2, and source/drain regions 13 by impurity cutting and widening, OV D-
UiOl p 14, Chengden erected di t 5 f are formed and completed.

この様に５ｉＪｊ板を用いた完全誘電体分囁半導体装直
の製作により低コストで＾連の半導体訣瀘が提供できる
効果がある。In this way, by directly manufacturing a completely dielectric semiconductor device using a 5iJj board, it is possible to provide a series of semiconductor devices at low cost.

【図面の簡単な説明】[Brief explanation of drawings]

４１図ｈ＞〜（ｇ）は不発明による完全誘電体分離Ｃ−
ＭＯ８ＩＯの製造工ａを成型断面図を用いて示したもの
である。 １・・・Ｂｉ基板、２．６・・・薄い８１０．膜、５．
７・・・”１３膜４Ｍ、４・・・下地Ｓ１０．側、５・
・・５ｌ−１８・・・！ｌ！亀体分ｂ・；蛇５１０８．
９・・・Ｐウェル、１Ｕ・・・Ｎウェル、１１・・・ゲ
ー）ＳｉＯ１１躊、１ノ・・・ケート両種、　　１５　
・・・拡散１−１　１４　・・・　ＣＶ　　１１　　・
　Ｓ　ｉ　０１　−１１５・・・Ａｔ配−０ 以　　　上 出願人　株式会社＃肋精工舎 代理人　弁珈士琺土　　務 第１図Figures 41 h> to (g) show complete dielectric separation C- due to uninvention.
The manufacturing process a of MO8IO is shown using a molding cross-sectional view. 1...Bi substrate, 2.6...Thin 810. membrane, 5.
7..."13 film 4M, 4...base S10. side, 5...
...5l-18...! l! Turtle body part b・; snake 5108.
9...P well, 1U...N well, 11...Ge) SiO11, 1 No...Both types of Kate, 15
... Diffusion 1-1 14 ... CV 11 ・
S i 01-115...At distribution-0 Applicant: #Koiseikosha Co., Ltd. Agent: Attorney Tsutomu Kodo Figure 1

Claims (1)

【特許請求の範囲】 １１１　８１基板表面Ｋに部分的に窓開けされた６１０
゜膜が形成され、該窓部およびＢ１０ｚ　）ｌ！Ｉ上に
は準結晶日ｉ展が形成され、前記窓部上の単結晶Ｓ１膜
は熱１１（ｔｌｊ　り１ｌｌｌｌ１体分噌５ｉｏｔ　ト
Ｌ、テ、ｉｌｌ　８ｒ：　下地８１０．幌と接して、前
記窓ｍｔ埋め込んで形成されている事１ｒ特命とする半
導体装置。 ＋２＋ｓｉ基板表面ＶＣは部分的に窓−けさｌしたＳ１
０．膜が形成され、該窓部およびＢ１０．膜上には単結
晶Ｂ１膜が形成され、＠記念部上の単結晶ｓｉｇに熱酸
化により誘電体分−８１０，として、１記下地８１０．
膜と接してｌｌ１ｌ記窓部を埋め込んで形成さｎている
事を％挙とする半導体装置の製造方法。[Claims] 111 81 Partially opened window 610 on substrate surface K
A film is formed and the window and B10z)l! A quasi-crystalline S1 film is formed on the window part, and the single crystal S1 film on the window part is heated by heat 11 (tlj ri 1 l l l l 1 body part 5 iot L, T, ill 8r: Underlayer 810. In contact with the hood, the above-mentioned A semiconductor device specially designed to be formed with a window mt buried in it. +2+Si substrate surface VC is partially windowed S1
0. A membrane is formed and the window and B10. A single-crystal B1 film is formed on the film, and the single-crystal sig on the memorial part is thermally oxidized to make the dielectric material -810.
A method of manufacturing a semiconductor device, comprising: burying and forming a window portion in contact with a film.
JP12952181A 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof Granted JPS5831552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12952181A JPS5831552A (en) 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12952181A JPS5831552A (en) 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS5831552A true JPS5831552A (en) 1983-02-24
JPH0420266B2 JPH0420266B2 (en) 1992-04-02

Family

ID=15011552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12952181A Granted JPS5831552A (en) 1981-08-18 1981-08-18 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS5831552A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020531A (en) * 1983-06-21 1985-02-01 ソシエテ・プール・レチユード・エ・ラ・フアブリカシオン・デ・シルキユイ・アンラグレ・スペシオー―ウ―・エフ・セー・イー・エス Method of producing insulating semiconductor element on semiconductor wafer
JPS6038830A (en) * 1983-08-12 1985-02-28 Oki Electric Ind Co Ltd Manufacture of semiconductor device
US5300448A (en) * 1991-02-01 1994-04-05 North American Philips Corporation High voltage thin film transistor having a linear doping profile and method for making

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5019439A (en) * 1973-04-09 1975-02-28
JPS5673697A (en) * 1979-11-21 1981-06-18 Hitachi Ltd Manufacture of single crystal thin film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5019439A (en) * 1973-04-09 1975-02-28
JPS5673697A (en) * 1979-11-21 1981-06-18 Hitachi Ltd Manufacture of single crystal thin film

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020531A (en) * 1983-06-21 1985-02-01 ソシエテ・プール・レチユード・エ・ラ・フアブリカシオン・デ・シルキユイ・アンラグレ・スペシオー―ウ―・エフ・セー・イー・エス Method of producing insulating semiconductor element on semiconductor wafer
US5387537A (en) * 1983-06-21 1995-02-07 Soclete Pour I'etude Et Al Fabrication De Circuits Integres Speciaux E.F.C.I.S. Process for manufacturing isolated semiconductor components in a semiconductor wafer
US5457338A (en) * 1983-06-21 1995-10-10 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux E.F.C.I.S. Process for manufacturing isolated semi conductor components in a semi conductor wafer
JPS6038830A (en) * 1983-08-12 1985-02-28 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH0451977B2 (en) * 1983-08-12 1992-08-20 Oki Electric Ind Co Ltd
US5300448A (en) * 1991-02-01 1994-04-05 North American Philips Corporation High voltage thin film transistor having a linear doping profile and method for making

Also Published As

Publication number Publication date
JPH0420266B2 (en) 1992-04-02

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