JPS5824948B2 - Manufacturing method of cross-wiring structure - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a cross wiring structure.

Conventionally, when wiring layers formed in an integrated circuit include intersections, a multilayer wiring structure is used with an insulating film interposed therebetween.

That is, as shown in FIG. 1, a lower wiring layer 3 is formed on an insulating layer 2 covering a surface of a semiconductor substrate, and an insulating film 4 is formed covering this lower wiring layer 3 and the insulating layer 2. The upper wiring layer 5 intersects with the lower wiring layer 3 via
is formed.

Incidentally, an integrated circuit intended for high frequency and high speed operation must reduce parasitic capacitance as much as possible, and the wiring structure described above is designed to have as few intersections as possible, and the insulating film 4 has a relative dielectric constant. By using a material coated with a thick material having a small value (generally S J 02 ), the capacitance between wiring layers at unavoidable intersections is reduced.

However, increasing the thickness of the insulating film 4 has the disadvantage that cracks may occur in the insulating film 4 itself, that it takes a long time to form the film, and that the heat applied at that time changes the characteristics of the semiconductor element. be.

In order to electrically draw out the lower wiring layer 3 to the surface of the insulating film 4, a process is required in which a contact hole must be formed in the insulating film 4.

Further, the insulating film 4 covering the upper surface of the lower wiring layer 3 has a step-like bulge, and in order to prevent the earth wiring layer 5 that intersects this bulge from being broken at the step portion, It was also necessary to take measures such as finishing the cross section of the wiring layer 3 or the insulating film 4 covering the lower wiring layer 3 into a tapered shape.

In view of the above points, the present invention was made in order to solve such problems and eliminate such drawbacks.The purpose of the present invention is to reduce the capacitance between each wiring, and the structure allows extremely easy crossing. An object of the present invention is to provide a method for manufacturing a wiring structure.

In order to achieve such an object, the present invention includes a step of forming a first wiring layer on an insulating substrate, a step of applying a photoresist to cover at least a region of the first wiring layer, and a step of applying a photoresist to cover at least a region of the first wiring layer. forming a side surface of the photoresist into an arc shape along the thickness direction by baking; forming a second wiring layer that intersects with the first wiring layer in the formation region of the photoresist;
The method includes a step of removing the photoresist.

The present invention will be described in detail below using Examples.

FIG. 2 is a configuration diagram showing an example of a cross wiring structure obtained by the method for manufacturing a cross wiring structure according to the present invention.

In order to facilitate understanding of the present invention, FIG. 2 will first be explained.

In the figure, there is a semiconductor substrate 1, the surface of which is coated with an insulating layer 2.

Then, on this insulating layer 2, a titanium film with a thickness of about 300 mm (
A lower wiring layer 3 is formed by sequentially laminating Ti) and gold (Au) having a film thickness of about 0.5 to 1 μm, for example, from the cover of the drawing to the back of the drawing.

On the other hand, an upper wiring layer 5 is formed in a direction intersecting the lower wiring layer 3 by sequentially laminating titanium with a thickness of about 300 mm and gold with a thickness of about 0.5 to 1 μm. At the intersection between the layer 3 and the upper wiring layer 5, the upper wiring layer 5 is spatially separated from the lower wiring layer 3 while crossing the lower wiring layer 3 in an arc shape.

An embodiment of a method for manufacturing such a cross-wiring structure is shown in FIGS. 3a" and 3d.

First, in FIG. 1A, a titanium layer with a thickness of approximately 300 μm and a gold layer with a thickness of approximately 0.5 to 1 μm are sequentially formed by vapor deposition over the entire area of the insulating layer 2 formed on the surface of the semiconductor substrate 1. do.

Then, the laminated metal layer thus formed is etched into the lower wiring layer 3 in a predetermined pattern by a well-known photoetching method.
form.

In the figure, the lower wiring layer 3 is formed from the surface of the paper to the back of the paper.

After that, a photoresist 6 (for example, AZ-1350J) is applied to a thickness of about 3 to 4 μm on the insulating layer 2 including the lower wiring layer 3.
Then, only the photoresist 6 sufficient to fully cover the lower wiring layer 3 is left, and the rest is removed by photolithography.

Next, the photoresist 6 is post-baked at 150 to 180°C.

In this way, the photoresist 6 is softened, and due to the surface tension generated at this time, the side surfaces of the photoresist 6 become arcuate along the thickness direction, as shown in the figure.

After that, a titanium layer with a thickness of about 300 and a thickness of about 0.5 to 1 μm is applied to the entire area of the insulating layer 2 including the photoresist 6.
gold layer and the like are sequentially formed by vapor deposition or the like.

Then, the laminated metal layer thus formed is etched into the upper wiring layer 5 in a predetermined pattern by a well-known photoetching method.
form.

In this case, the temperature of the radiant heat received during the formation of the laminated metal layer is lower than the heat required for the post-baking, so the photoresist 6 does not soften again and maintains its shape, and the upper wiring layer 5 As shown in FIG.
It begins to straddle itself with a.

Next, the photoresist 6 is completely removed by immersing it in a suitable removal solution.

By doing this, the upper wiring layer 5 has an arc-shaped base 5a and crosses over the lower wiring layer 3, as shown in FIG. Becomes insulated.

According to the cross wiring structure obtained by the method for manufacturing a cross wiring structure of the present invention configured as described above, insulation between the lower wiring layer 3 and the upper wiring layer 5 is achieved through the air layer, and the insulation between the lower wiring layer 3 and the upper wiring layer 5 is achieved through the air layer. The dielectric constant is extremely small, approximately 1, and the distance between the upper wiring layer 5 and the lower wiring layer 3 at the intersection is several microns.
m or more, the capacitance of each wiring layer can be reduced to 1/10 or less of the conventional capacitance, which is preferable for cross-wiring of integrated circuits intended for high-frequency and high-speed operation.

In addition, during the manufacturing process, the photoresist 6 required for insulation from the lower wiring layer 3 and the upper wiring layer 5 is formed by coating and then post-baked, which does not require heat treatment that changes the characteristics of the semiconductor element. figure,
Furthermore, since the lower wiring layer 3 and the upper wiring layer 5 are only overlapped at the intersection, and the electrode extension part can be taken out on the insulating layer 2, a contact hole for drawing out the lower wiring layer is provided in the insulating layer as in the conventional method. There will be no need.

In addition, since the side surfaces of the photoresist 6 covering the lower wiring layer 3 become arcuate along the thickness direction during post-baking after coating (see FIG. 3C), when forming the upper wiring layer 5, There is no need to worry about step breaks occurring at step portions, and the upper wiring layer 5 formed on the surface of the photoresist 6 and intersecting the lower wiring layer 3 has an arcuate base after the photoresist 6 is removed. Since it extends over the lower wiring layer 5, it can have a large mechanical strength against external impacts such as ultrasonic cleaning, centrifugal force caused by a spinner, and thermal expansion.

In this embodiment, the photoresist 6 covering the lower wiring layer 3 is formed by photolithography after the coating process, but after that, a new photoresist is coated and the cross section is formed by photolithography. Alternatively, a pyramid-shaped photoresist having a stepped structure may be formed, and then post-baking may be performed.

By doing this, the lower wiring layer 3 and the upper wiring layer 5
This makes it possible to increase the separation distance between the two.

In this embodiment, when the photoresist 6 is formed, it is made to sufficiently cover the entire area of the lower wiring layer 3.
The photoresist 6 is not limited to this, and the photoresist 6 may be formed only in the region of the lower wiring layer 3 at the intersection with the upper wiring layer 5.

In this case, a vapor-deposited metal layer formed after the formation of the photoresist 6 is deposited on the lower wiring layer 3 exposed from the photoresist 6. After that, the vapor-deposited metal layer is etched in the thickness direction with precision. By doing this well, the lower wiring layer 3 and the upper wiring layer 5 can be formed in a predetermined pattern.

Furthermore, although this embodiment describes cross wiring in an integrated circuit, it is not limited to integrated circuits, and can be applied to all general cross wiring (particularly microfabricated fine wires).

As described above, according to the method for manufacturing a cross wiring structure according to the present invention, the capacitance between customer wiring layers can be reduced and the manufacturing thereof can be made extremely easy.

[Brief explanation of drawings]

Figure 1 is a configuration diagram showing an example of a conventional cross-wiring structure;
3A to 3D are block diagrams showing an embodiment of a cross wiring structure obtained by the method for manufacturing a cross wiring structure according to the present invention and a method for manufacturing the cross wiring structure, respectively. 1... Semiconductor substrate, 2... Insulating layer, 3
... lower wiring layer, 4 ... insulating film, 5.
. . . Upper wiring layer, 6 . . . Photoresist.

Claims (1)

[Claims] 1. A step of forming a first wiring layer on an insulating substrate, a step of applying a photoresist covering at least a region of the first wiring layer, and a step of baking the photoresist to increase the thickness of the side surface of the photoresist. The step of forming a circular arc along the horizontal direction, the step of forming a second wiring layer that intersects with the first wiring layer in the area where the photoresist is formed, and the step of removing the photoresist. A method for manufacturing a distinctive cross-wiring structure.