JPS61144034A - Manufacture of transfer bump substrate - Google Patents

Manufacture of transfer bump substrate

Info

Publication number
JPS61144034A
JPS61144034A JP59265732A JP26573284A JPS61144034A JP S61144034 A JPS61144034 A JP S61144034A JP 59265732 A JP59265732 A JP 59265732A JP 26573284 A JP26573284 A JP 26573284A JP S61144034 A JPS61144034 A JP S61144034A
Authority
JP
Japan
Prior art keywords
bumps
film
insulation film
pinholes
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59265732A
Other languages
Japanese (ja)
Inventor
Yoshifumi Kitayama
北山　喜文
Shuichi Murakami
修一 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59265732A priority Critical patent/JPS61144034A/en
Publication of JPS61144034A publication Critical patent/JPS61144034A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

PURPOSE:To realize efficient plating operation and to enable bumps to be produced uniformly in thickness among various lots, by providing an insulation film without pinholes for assuring that only the required region is electrically plated during the partial electric plating operation. CONSTITUTION:A transparent conductor film 2 is provided on the principal surface of a transparent glass substrate 1 by vapor deposition or the like. Subsequently, a transparent insulation film 3a of SiO2 or the like is deposited thereon, and the conductor film 2 exposed in pinholes 6 produced in the insulation film 3a is removed by etching. Another insulation film 3b is provided thereon. The insulation films 3a and 3b are provided with fine holes 4 in the regions corresponding to electrodes of a semiconductor element. Bumps 5 of Au or the like are formed on the conductor film 2 exposed in these fine holes 4 by the electric plating so as to have a thickness of 10-40mum. In this manner, no undesired bumps but the normal bumps 5 are produced during the electric plating process. Further, since virtually identical electric current is applied to the transfer bump substrates, variability of bump thickness can be reduced among various lots.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はフィルムキャリア方式およびフリ・ツブチップ
方式による半導体素子の組立てにおいて半導体素子の電
極部あるいはフィルムキャリアのリード部へ金属突起物
を供給するだめの転写ノ（ンプ基板の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the transfer of metal protrusions to the electrode portions of semiconductor devices or the lead portions of film carriers in the assembly of semiconductor devices using the film carrier method and the free-chip method. The present invention relates to a method for manufacturing a pump board.

従来例の構成とその問題点 従来の金属突起物基板においては、第１図にその具体例
を示すように、ガラス、シリコン、アルミナ基板のよう
な絶縁基板１上に蒸着や印刷法によってＴｉ／Ｐｄ、Ｔ
ｉ／Ｐｔ、Ａｕ、ＩＴＯなどの導電膜２を形成した後、
さらにその上にＳ　Ｌ０２などの絶縁膜３を形成して半
導体素子の電極部に対応するように微小孔４をあけて、
微小孔４で露出している導電膜２にＡｕなどのような金
属突起物６を電気メ・フキによ９１０〜４０μｍ形成し
ていた。そして、この金属突起物５のみをフィルムキャ
リアのリードの先端部に熱圧着して転写させていた。こ
のような構成では、絶縁膜３にピンホール６が発生して
電気メッキのときに電流密度が安定しにくくなり、所定
の金属突起物５の高さが得られなくなるという問題があ
った。また、バンプ６をフィルムキャリアのリードの先
端部に熱圧着方式で転写したときにピンホール６から発
生したバンプ７がついて不良になるという問題もあった
。Structure of the conventional example and its problems In the conventional metal protrusion substrate, as shown in a specific example in FIG. Pd,T
After forming the conductive film 2 of i/Pt, Au, ITO, etc.
Furthermore, an insulating film 3 such as S L02 is formed on top of the insulating film 3, and micro holes 4 are made to correspond to the electrode parts of the semiconductor element.
Metal protrusions 6 made of Au or the like were formed with a thickness of 910 to 40 μm on the conductive film 2 exposed through the microholes 4 using electric wire. Then, only the metal protrusion 5 was transferred by thermocompression bonding to the tip of the lead of the film carrier. This configuration has the problem that pinholes 6 are generated in the insulating film 3, making it difficult to stabilize the current density during electroplating, and making it impossible to obtain a predetermined height of the metal projections 5. Further, when the bumps 6 were transferred to the leading ends of the leads of the film carrier by thermocompression bonding, there was a problem in that the bumps 7 generated from the pinholes 6 were attached, resulting in defects.

発明の目的 本発明は上記欠点を除去するものであり、絶縁膜にピン
ホールを無くす方法を提供するものであるＯ 発明の構成 本発明は、導電膜を形成した絶縁基板で、前記導電膜上
にスパッタリング法、蒸着法などによって半導体素子の
電極部に対応するように微小孔を設けた８１０２等の絶
縁膜を形成したのち、前記絶縁膜に発生したピンホール
部に露出している前記導電膜を工・１チング加工で除去
したあと、再び絶縁膜に形成して半導体素子の電極部に
対応するように微小孔を設けたのち電気メッキでＡｕ等
のバンプを形成する工程からなり、電気メッキしてもＳ
　ｓ　０２膜のピンホール部にはメッキされないので常
に一定の高さのバンプを得ることができる。また、パン
ダをフィルムキャリアのリードの先端部に転写したとき
にピンホールによるバンプがついて不良忙なるというこ
とがないので有利である。OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned drawbacks and provides a method for eliminating pinholes in an insulating film. After forming an insulating film such as 8102 with microholes corresponding to the electrode portions of the semiconductor element by sputtering, vapor deposition, etc., the conductive film is exposed in the pinholes generated in the insulating film. The process consists of removing bumps of Au etc. by electroplating, forming them on the insulating film again, making micro holes corresponding to the electrodes of the semiconductor element, and then forming bumps of Au etc. by electroplating. Even if S
Since the pinhole portion of the s02 film is not plated, bumps of a constant height can always be obtained. Further, when the panda is transferred to the leading end of the lead of the film carrier, there is no possibility of bumps caused by pinholes resulting in defects, which is advantageous.

実施例の説明 以下、本発明の一実施例について図により説明する。ま
ず、透明なガラス基板１の一生面に透明な導電膜２を蒸
着法などによって形成したのち、Ｓ　Ｌ０２などのよう
な透明な絶縁膜３ａを形成して、絶縁膜３ａに生じたピ
ンホール６の部分の導電膜２をエツチングで除去したの
ち、再び絶縁膜３ｂを形成したのち、半導体素子の電極
に対応するように絶縁膜３ａ、３ｂに微小孔４をあげる
。そののち、微小孔４の部分に露出している導電膜２に
Ａｕなどのようなバンプ６を電気メッキにより１０〜４
０μｍ形成する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, a transparent conductive film 2 is formed on the entire surface of a transparent glass substrate 1 by a vapor deposition method, and then a transparent insulating film 3a such as S L02 is formed to remove the pinholes 6 generated in the insulating film 3a. After removing the portion of the conductive film 2 by etching, and forming the insulating film 3b again, micro holes 4 are formed in the insulating films 3a and 3b so as to correspond to the electrodes of the semiconductor element. After that, bumps 6 made of Au or the like are formed by electroplating on the conductive film 2 exposed in the microholes 4.
0 μm is formed.

以上のように本実施例によれば、絶縁膜３ａにピンホー
ル６が生じてもエツチングでその下地の導電膜２が除去
されて、さらに絶縁膜３ｂでコーティングされるために
電気メッキのときに正規のＩζζダグ以外に異常なバン
プは発生しない。また、電流の大きさも、転写バンプ基
板の間で差がなくなるのでロット間のバンプの高さのバ
ラツキも少なくなる。As described above, according to this embodiment, even if a pinhole 6 is formed in the insulating film 3a, the underlying conductive film 2 is removed by etching and is further coated with the insulating film 3b, so that it can be removed during electroplating. No abnormal bumps occur other than the regular Iζζ tag. Further, since there is no difference in the magnitude of the current between the transfer bump substrates, variations in bump height between lots are also reduced.

発明の効果 このように本発明は、絶縁膜にピンホールがないため、
部分電気メッキしても所定の場所以外にメ、フキされな
いために効率よくメ・ンキできるとともに、バンプ高さ
をロフト間で均一にできるという点で非常に効果がある
。Effects of the Invention As described above, the present invention has no pinholes in the insulating film, so
Even if partial electroplating is performed, it is very effective in that the bump height can be made uniform among the lofts, as it is not only possible to apply the metal to areas other than the predetermined areas.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の転写バンプ基板の断面図、第２図は本発
明の一実施例における転写バンプ基板の断面図である。 １・・・・・・絶縁基板、２・・・・・・導電膜、３．
３ａ、３ｂ・・・・・・絶縁膜、４・・・・・・微小孔
、６・・・・・・バンプ、６・・・・・・・・・ピンホ
ール、７・・・・・・バンプ。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第１
図 第２図FIG. 1 is a sectional view of a conventional transfer bump substrate, and FIG. 2 is a sectional view of a transfer bump substrate according to an embodiment of the present invention. 1... Insulating substrate, 2... Conductive film, 3.
3a, 3b...Insulating film, 4...Minor hole, 6...Bump, 6...Pinhole, 7... ·bump. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2

Claims (1)

【特許請求の範囲】[Claims] 導電膜を形成した絶縁基板で、前記導電膜上にスパッタ
リング法、蒸着法などによってＳｉＯ＿２等の絶縁膜を
形成したのち、前記絶縁膜に発生したピンホール部に露
出している前記導電膜をエッチング加工で除去したあと
、再び絶縁膜を形成して半導体素子の電極部に対応する
ように微小孔を設けたのち電気メッキでＡｕ等のバンプ
を形成する工程からなる転写バンプ基板の製造方法。With an insulating substrate on which a conductive film is formed, an insulating film such as SiO_2 is formed on the conductive film by sputtering, vapor deposition, etc., and then the conductive film exposed in the pinholes generated in the insulating film is etched. A method for producing a transfer bump substrate, which comprises the steps of removing it by processing, forming an insulating film again, forming microholes to correspond to the electrode portions of the semiconductor element, and then forming bumps of Au or the like by electroplating.
JP59265732A 1984-12-17 1984-12-17 Manufacture of transfer bump substrate Pending JPS61144034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59265732A JPS61144034A (en) 1984-12-17 1984-12-17 Manufacture of transfer bump substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59265732A JPS61144034A (en) 1984-12-17 1984-12-17 Manufacture of transfer bump substrate

Publications (1)

Publication Number Publication Date
JPS61144034A true JPS61144034A (en) 1986-07-01

Family

ID=17421225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59265732A Pending JPS61144034A (en) 1984-12-17 1984-12-17 Manufacture of transfer bump substrate

Country Status (1)

Country Link
JP (1) JPS61144034A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0792463A4 (en) * 1994-11-15 1998-06-24 Formfactor Inc Mounting spring elements on semiconductor devices, and wafer-level testing methodology
EP0859686A4 (en) * 1995-05-26 1998-11-11 Formfactor Inc Fabricating interconnects and tips using sacrificial substrates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0792463A4 (en) * 1994-11-15 1998-06-24 Formfactor Inc Mounting spring elements on semiconductor devices, and wafer-level testing methodology
EP0859686A4 (en) * 1995-05-26 1998-11-11 Formfactor Inc Fabricating interconnects and tips using sacrificial substrates

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