JP3331635B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP3331635B2
JP3331635B2 JP26383492A JP26383492A JP3331635B2 JP 3331635 B2 JP3331635 B2 JP 3331635B2 JP 26383492 A JP26383492 A JP 26383492A JP 26383492 A JP26383492 A JP 26383492A JP 3331635 B2 JP3331635 B2 JP 3331635B2
Authority
JP
Japan
Prior art keywords
layer
electrode
semiconductor device
circuit pattern
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP26383492A
Other languages
Japanese (ja)
Other versions
JPH06120226A (en
Inventor
俊宏 沢本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP26383492A priority Critical patent/JP3331635B2/en
Publication of JPH06120226A publication Critical patent/JPH06120226A/en
Application granted granted Critical
Publication of JP3331635B2 publication Critical patent/JP3331635B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体素子およびその
実装体に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a package thereof.

【0002】[0002]

【従来の技術】半導体素子1の能動面を外部回路基板6
と対向させ、前記半導体素子1の電極を前記外部回路基
板6のパターン5上に接続するという、いわゆるフリッ
プチップ実装方式に使用される半導体素子の電極は、従
来、図3のように、Al電極層2上に、スパッタリング
により設けたCr層7及びCu層8の、いわゆるバリア
メタル層を介し、電解メッキによりCuメッキ層9を3
〜4μm程度設け、さらに、100μm程度の半田を施
し突起状にした、いわゆる半田バンプの電極が主流であ
った。
2. Description of the Related Art An active surface of a semiconductor device 1 is connected to an external circuit board 6.
Conventionally, an electrode of a semiconductor element used in a so-called flip-chip mounting method of connecting the electrode of the semiconductor element 1 to the pattern 5 of the external circuit board 6 is an Al electrode, as shown in FIG. A Cu plating layer 9 is formed on the layer 2 by electrolytic plating through a so-called barrier metal layer of a Cr layer 7 and a Cu layer 8 provided by sputtering.
Electrodes of so-called solder bumps, which are provided in a thickness of about 4 μm and are further provided with a solder of about 100 μm to form projections, are mainly used.

【0003】[0003]

【発明が解決しようとする課題】しかし、前述の従来技
術でのハンダバンプの電極では、図3で示したCuメッ
キ層9の厚さが3〜4μmと非常に薄いために、フリッ
プチップ実装の際、図4のように、Cuメッキ層9と外
部回路基板6とのパターンとの間のギャップ10が大き
くなる。例えば、半導体素子1にかかる圧力が小さい場
合、図4(a)のように、半田4による接続が不十分で
あるのに対し、かかる圧力が大きい場合、図4(b)の
ように、半田の流れ出しにより、パターン間でショート
する可能性が高くなるので、回路パターンの細密化が困
難になるという問題点を有する。そこで本発明はこのよ
うな問題点を解決するもので、その目的とするところ
は、前記ギャップの均一化による半導体装置の品質安定
化及びハンダバンプ製作工程の簡素化、低コスト化を提
供するところにある。
However, since the thickness of the Cu plating layer 9 shown in FIG. 3 is very thin, 3 to 4 μm, in the above-mentioned solder bump electrode of the prior art, the flip-chip mounting is difficult. As shown in FIG. 4, the gap 10 between the Cu plating layer 9 and the pattern of the external circuit board 6 increases. For example, when the pressure applied to the semiconductor element 1 is small, the connection by the solder 4 is insufficient as shown in FIG. 4A, while when the applied pressure is large, the solder 4 is connected as shown in FIG. As a result, the possibility of short-circuiting between the patterns increases, which makes it difficult to miniaturize the circuit pattern. Therefore, the present invention solves such a problem, and an object of the present invention is to provide stabilization of the quality of a semiconductor device and simplification of a solder bump manufacturing process and cost reduction by uniforming the gap. is there.

【0004】[0004]

【課題を解決するための手段】(1) 本発明の半導体
装置は、回路パターンを有する外部回路基板と、前記回
路パターンに電気的に接続された電極を有し、前記外部
回路基板に向けて前記電極を有する表面が配置された半
導体素子と、を含む半導体装置であって、前記電極は、
Ni層と半田層とを含み、前記半田層が前記回路パター
ンに接するように配置されており、前記半田層は、少な
くとも前記回路パターンの側面に被着していることを特
徴とする。 (2) 本発明の半導体装置は、回路パターンを有する
外部回路基板と、前記回路パターンに電気的に接続され
た電極を有し、前記外部回路基板に向けて前記電極を有
する表面が配置された半導体素子と、を含む半導体装置
であって、前記電極は、Ni層と前記Ni層の上方に設
けられた半田層とを含み、前記半田層が前記回路パター
ンに接して配置されており、前記Ni層は、前記回路パ
ターンの少なくとも一部に接触していることを特徴とす
る。 (3) 本発明の半導体装置は、上記(1)又は(2)
に記載の半導体装置において、前記Ni層の厚みは、前
記半田層の厚みよりも厚いことを特徴とする。 (4) 本発明の半導体装置は、上記(1)から(3)
のいずれかに記載の半導体装置において、前記Ni層
は、無電解メッキにより形成されてなることを特徴とす
る。 (5) 本発明の半導体装置は、上記(1)から(4)
に記載の半導体装置において、前記電極は、前記半導体
素子の表面に設けられた電極層を含み、前記Ni層は、
前記電極層の表面に接して設けられることを特徴とす
る。 (6) 本発明の半導体装置は、上記(1)から(5)
のいずれかに記載の半導体装置において、前記電極は、
前記半導体素子の表面に露出している部分の全面が前記
半田層で覆われていることを特徴とする。 (7) 本発明の半導体装置の製造方法は、Ni層と前
記Ni層の上方に設けられた半田層とを含む電極を有す
る半導体素子を、前記電極を有する表面と回路パターン
を有する外部回路基板とを対向させて配置する工程と、
少なくとも前記回路パターンの側面に前記半田層を被着
させ、前記電極と前記回路パターンとを熱圧着して、前
記電極と前記回路パターンとを電気的に接続する工程
と、を有することを特徴とする。 (8) 本発明の半導体装置の製造方法は、Ni層と前
記Ni層の上方の半田層とを含む電極を有する半導体素
子を、前記電極を有する表面と回路パターンを有する外
部回路基板とを対向させて配置する工程と、前記電極と
前記回路パターンとを熱圧着して、少なくとも前記Ni
層を前記回路パターンの少なくとも一部に接触させて、
前記電極と前記回路パターンとを電気的に接続する工程
と、を有することを特徴とする。 (9) 本発明の半導体装置の製造方法は、上記(7)
又は(8)に記載の半導体装置の製造方法において、さ
らに、前記半導体素子と前記外部回路基板とを対向させ
て配置する工程の前に、前記半導体素子の表面に前記半
導体素子の前記電極を設ける工程を有し、前記電極を設
ける工程において、前記Ni層は無電解メッキ法により
形成され、前記半田層はディッピングにより形成される
ことを特徴とする。 (10) 本発明の半導体装置の製造方法は、半導体素
子の表面の電極層の上方にNi層を設ける工程と、半田
浴に前記半導体素子を浸漬する工程と、等速で前記半田
浴から前記半導体素子を引き上げ、前記Ni層の上方に
前記Ni層よりも薄い前記半田層を設ける工程と、を有
することを特徴とする。 (11) 本発明の半導体装置の製造方法は、上記(1
0)記載の半導体装置の製造方法において、前記Ni層
の上方に前記半田層を設ける工程において、前記半導体
素子の前記電極が設けられた表面にNパージした熱風
を吹き付け、前記半導体素子の前記電極以外に付着した
半田を除去する工程を有することを特徴とする。
(1) A semiconductor device according to the present invention includes an external circuit board having a circuit pattern, and an electrode electrically connected to the circuit pattern. A semiconductor element on which a surface having the electrode is disposed, wherein the electrode comprises:
It is characterized by including a Ni layer and a solder layer, wherein the solder layer is disposed so as to be in contact with the circuit pattern, and the solder layer is attached to at least a side surface of the circuit pattern. (2) The semiconductor device of the present invention has an external circuit board having a circuit pattern, and an electrode electrically connected to the circuit pattern, and has a surface having the electrode disposed toward the external circuit board. A semiconductor element, wherein the electrode includes a Ni layer and a solder layer provided above the Ni layer, wherein the solder layer is disposed in contact with the circuit pattern; The Ni layer is in contact with at least a part of the circuit pattern. (3) The semiconductor device according to the present invention is characterized in that (1) or (2)
Wherein the thickness of the Ni layer is thicker than the thickness of the solder layer. (4) The semiconductor device of the present invention includes the above (1) to (3)
The semiconductor device according to any one of the above, wherein the Ni layer is formed by electroless plating. (5) The semiconductor device of the present invention includes the above (1) to (4)
In the semiconductor device described in the above, the electrode includes an electrode layer provided on the surface of the semiconductor element, the Ni layer,
It is characterized by being provided in contact with the surface of the electrode layer. (6) The semiconductor device of the present invention includes the above (1) to (5)
In the semiconductor device according to any one of the above,
The entire surface of the portion exposed on the surface of the semiconductor element is covered with the solder layer. (7) A method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor element having an electrode including a Ni layer and a solder layer provided above the Ni layer by using an external circuit board having a surface having the electrode and a circuit pattern. And a step of disposing them facing each other;
Attaching the solder layer to at least a side surface of the circuit pattern, thermocompression bonding the electrode and the circuit pattern, and electrically connecting the electrode and the circuit pattern. I do. (8) In the method of manufacturing a semiconductor device according to the present invention, the semiconductor element having the electrode including the Ni layer and the solder layer above the Ni layer is opposed to the surface having the electrode and the external circuit board having the circuit pattern. And placing the electrode and the circuit pattern by thermocompression bonding to at least the Ni
Contacting a layer with at least a portion of the circuit pattern,
Electrically connecting the electrode and the circuit pattern. (9) The method of manufacturing a semiconductor device according to the present invention includes the method (7) described above.
Alternatively, in the method of manufacturing a semiconductor device according to (8), the electrode of the semiconductor element is provided on a surface of the semiconductor element before the step of arranging the semiconductor element and the external circuit board so as to face each other. A step of providing the electrode, wherein the Ni layer is formed by an electroless plating method, and the solder layer is formed by dipping. (10) The method of manufacturing a semiconductor device according to the present invention includes the steps of: providing a Ni layer above the electrode layer on the surface of the semiconductor element; immersing the semiconductor element in a solder bath; Lifting the semiconductor element and providing the solder layer thinner than the Ni layer above the Ni layer. (11) The method of manufacturing a semiconductor device according to the present invention includes the method (1) described above.
0) In the method of manufacturing a semiconductor device according to the aspect of the invention, in the step of providing the solder layer above the Ni layer, hot air purged with N 2 is blown onto a surface of the semiconductor element on which the electrode is provided, and The method is characterized in that the method includes a step of removing solder attached to portions other than the electrodes.

【0005】[0005]

【作用】本発明の上記の構成によれば、無電解メッキで
厚高に形成したNiメッキ層上に、半田をディッピング
することにより、ボンディングの際、突起状のNiメッ
キ層と外部回路基板のパターンが接触し、突起状のNi
メッキ層が、ギャップを保持するため、半導体素子と外
部回路基板との間のギャップが均一化される。
According to the above construction of the present invention, the Ni plating layer formed thick by electroless plating is dipped with solder to form a protrusion between the Ni plating layer and the external circuit board during bonding. The pattern comes in contact with the protrusion Ni
Since the plating layer maintains the gap, the gap between the semiconductor element and the external circuit board is made uniform.

【0006】[0006]

【実施例】以下、本発明の1実施例を、図1、図2及び
図4により説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

【0007】半導体素子1の電極は、はじめに前処理と
して、Al電極層2表面を洗浄するため、前記半導体素
子1表面にUV照射(照射時間2分)及びArプラズマ
(100W・5分)を施す。さらに、この半導体素子1
を、パラジウム濃度0.03g/l、液温5℃の塩化パ
ラジウム溶液中に2分間浸漬させ、Al電極層2表面を
活性化させる。活性化した後、直ちに、Niイオン濃度
3.0g/l(pH5.5)、液温65℃の無電解Ni
メッキ液中に、2時間静止状態で浸漬させ、厚さ15μ
m程度のNiメッキ層3を設ける。さらに、230℃に
加熱した半田浴(半田組成;Sn:Pb=6:4)中
に、半導体素子1を、能動面と液面が平行になる状態で
1〜2分浸漬させた後、ゆっくり等速で引き上げること
により、Niメッキ層3上に厚さ3〜4μmの半田層4
を形成することができる。このとき、半導体素子1を等
速で引き上げながら、N2でパージした熱風を浴外から
出た前記半導体素子1の能動面に吹きつけ、電極部分以
外に付着した余分な半田を払い落とす。このとき、Ni
メッキ層3が15μmと比較的厚く、しかもバンプ状に
形成されているため、重力及び表面張力の作用により、
半田層4は、バンプ状のNiメッキ層3表面を3〜4μ
mの厚みでコーティングされた状態で形成されることに
なる。このようにして製作した半田バンプを有する半導
体素子1を、外部回路基板6と対向させ、前記半導体素
子の電極を、パターン5上に熱圧着(条件:250℃,
5.0g/bump)により接続すると、図2のように、良
好な接合状態が得られる。図4に示した従来例と比較し
てもわかるように、従来は、半導体素子1のAl電極層
2上に3〜4μmと比較的薄く電解メッキされたCuメ
ッキ層9と外部回路基板6上のパターン5とが、半田を
介して接続されていたため、前記半導体素子1と前記外
部回路基板6との間のギャップ10が不均一になり、例
えば、前記半導体素子1に加える熱圧着条件の圧力が
「2.0g/bump」と小さかった場合、図4(a)のよ
うに、接続が不十分になったり、逆に、加える圧力が
「15g/bump」と大きかった場合、図4(b)のよう
に半田の流れ出しによるパターン間のショートを引き起
こす原因となった。ところが、本発明の場合は、熱圧着
の際、図2のようにバンプ状のNiメッキ層3とパター
ン5とが接触するため、ギャップ10を均一に保つこと
ができると同時に、半田層4が、3〜4μmの厚さで、
前記Niメッキ層上をコーティングするように形成され
ているため、半田量の調節が容易になり、半田の流れ出
しによるパターン間のショートを防ぐことができる。
The electrodes of the semiconductor element 1 are first subjected to UV irradiation (irradiation time of 2 minutes) and Ar plasma (100 W / 5 minutes) on the surface of the semiconductor element 1 to clean the surface of the Al electrode layer 2 as a pretreatment. . Further, the semiconductor element 1
Is immersed in a palladium chloride solution having a palladium concentration of 0.03 g / l and a liquid temperature of 5 ° C. for 2 minutes to activate the surface of the Al electrode layer 2. Immediately after activation, electroless Ni at a Ni ion concentration of 3.0 g / l (pH 5.5) and a liquid temperature of 65 ° C.
Immerse in a plating solution for 2 hours in a static state, and
A nickel plating layer 3 of about m is provided. Further, the semiconductor element 1 is immersed in a solder bath (solder composition; Sn: Pb = 6: 4) heated to 230 ° C. for 1 to 2 minutes with the active surface and the liquid surface parallel to each other, and then slowly. By pulling up at a constant speed, the solder layer 4 having a thickness of 3 to 4 μm is formed on the Ni plating layer 3.
Can be formed. At this time, while pulling up the semiconductor element 1 at a constant speed, hot air purged with N 2 is blown to the active surface of the semiconductor element 1 which has come out of the bath, and excess solder attached to portions other than the electrode portions is wiped off. At this time, Ni
Since the plating layer 3 is relatively thick as 15 μm and is formed in the shape of a bump, due to the action of gravity and surface tension,
The solder layer 4 covers the surface of the bump-shaped Ni plating layer 3 by 3 to 4 μm.
It is formed in a state coated with a thickness of m. The semiconductor element 1 having the solder bumps manufactured as described above is opposed to the external circuit board 6, and the electrodes of the semiconductor element are thermocompression-bonded onto the pattern 5 (condition: 250 ° C.,
When the connection is made at 5.0 g / bump, a good bonding state is obtained as shown in FIG. As can be seen from comparison with the conventional example shown in FIG. 4, conventionally, a Cu plating layer 9 which is relatively thinly plated by 3 to 4 μm on the Al electrode layer 2 of the semiconductor element 1 and the external circuit board 6 Since the pattern 5 is connected via solder, the gap 10 between the semiconductor element 1 and the external circuit board 6 becomes non-uniform. 4A is small as "2.0 g / bump", the connection is insufficient as shown in FIG. 4A, and conversely, if the applied pressure is large as "15 g / bump", FIG. ), Causing the short circuit between the patterns due to the outflow of the solder. However, in the case of the present invention, at the time of thermocompression bonding, the bump-shaped Ni plating layer 3 and the pattern 5 come into contact with each other as shown in FIG. With a thickness of 3-4 μm,
Since it is formed so as to coat the Ni plating layer, the amount of solder can be easily adjusted, and short-circuiting between patterns due to the flow of solder can be prevented.

【0008】[0008]

【発明の効果】以上の説明から明らかなように、本発明
は、半導体素子のAl電極層上にNiメッキ層を厚く形
成することにより、フリップチップ実装方式による接続
の際、半導体素子と外部回路基板との間のギャップが均
一になると同時に、半田量の調節が容易になり、半田の
流れ出しによるパターン間のショートを防止できること
から、品質の良い半導体装置を得ることができる。さら
に、半田バンプ製作工程に関しても、従来のバンプ状電
極の製作工程と比較して、本発明の半田バンプには、蒸
着工程やフォト工程がないことや、金属バンプの形成
を、機械及び装置の点で、比較的安価な無電解メッキ法
で行なうことから、製作工程の簡素化ならびに低コスト
化を図ることができる。
As is apparent from the above description, the present invention provides a semiconductor device and an external circuit at the time of connection by flip-chip mounting by forming a thick Ni plating layer on the Al electrode layer of the semiconductor device. At the same time as the gap between the substrate and the substrate becomes uniform, the adjustment of the amount of solder is facilitated, and short circuit between the patterns due to the flow of the solder can be prevented, so that a high quality semiconductor device can be obtained. Furthermore, as for the solder bump manufacturing process, compared to the conventional bump-shaped electrode manufacturing process, the solder bump of the present invention does not have a vapor deposition process and a photo process, and the formation of metal bumps requires a machine and an apparatus. In this regard, since the electroless plating method is used, which is relatively inexpensive, the manufacturing process can be simplified and the cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のフリップチップ実装用半導体素子のハ
ンダバンプの断面図。
FIG. 1 is a cross-sectional view of a solder bump of a flip-chip mounting semiconductor device of the present invention.

【図2】本発明のハンダバンプによりフリップチップ実
装された半導体装置の断面図。
FIG. 2 is a cross-sectional view of a semiconductor device flip-chip mounted with solder bumps according to the present invention.

【図3】従来のフリップチップ実装用半導体素子のハン
ダバンプの断面図。
FIG. 3 is a sectional view of a solder bump of a conventional flip-chip mounting semiconductor element.

【図4】従来のハンダバンプによりフリップチップ実装
された半導体装置の断面図。 (a) 半導体素子に加える圧力が小さい場合の断面
図。 (b) 半導体素子に加える圧力が大きい場合の断面
図。
FIG. 4 is a cross-sectional view of a conventional semiconductor device that is flip-chip mounted with solder bumps. (A) Sectional view when the pressure applied to the semiconductor element is small. (B) Sectional view when the pressure applied to the semiconductor element is large.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 Al電極層 3 Niメッキ層 4 半田 5 パターン 6 外部回路基板 7 Cr蒸着層 8 Cu蒸着層 9 Cuメッキ層 10 ギャップ REFERENCE SIGNS LIST 1 semiconductor element 2 Al electrode layer 3 Ni plating layer 4 solder 5 pattern 6 external circuit board 7 Cr deposited layer 8 Cu deposited layer 9 Cu plated layer 10 gap

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−164343(JP,A) 特開 昭64−7542(JP,A) 特開 平2−276249(JP,A) 特開 平1−187948(JP,A) 特開 平2−224335(JP,A) 特開 平2−296336(JP,A) 特開 平4−22131(JP,A) 実開 昭50−4666(JP,U) 実開 昭50−30662(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-164343 (JP, A) JP-A-64-7542 (JP, A) JP-A-2-276249 (JP, A) JP-A-1- 187948 (JP, A) JP-A-2-224335 (JP, A) JP-A-2-296336 (JP, A) JP-A-4-22131 (JP, A) Japanese Utility Model Laid-Open No. 50-4666 (JP, U) 50-50 (JP, U) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/60

Claims (11)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 回路パターンを有する外部回路基板と、 前記回路パターンに電気的に接続された電極を有し、前
記外部回路基板に向けて前記電極を有する表面が配置さ
れた半導体素子と、を含む半導体装置であって、 前記電極は、Ni層と半田層とを含み、前記半田層が前
記回路パターンに接するように配置されており、 前記半田層は、少なくとも前記回路パターンの側面に被
着していることを特徴とする半導体装置。
1. An external circuit board having a circuit pattern, and a semiconductor element having an electrode electrically connected to the circuit pattern and having a surface having the electrode facing the external circuit board. A semiconductor device, wherein the electrode includes a Ni layer and a solder layer, the solder layer is disposed so as to be in contact with the circuit pattern, and the solder layer is attached to at least a side surface of the circuit pattern. A semiconductor device characterized in that:
【請求項2】 回路パターンを有する外部回路基板と、 前記回路パターンに電気的に接続された電極を有し、前
記外部回路基板に向けて前記電極を有する表面が配置さ
れた半導体素子と、を含む半導体装置であって、 前記電極は、Ni層と前記Ni層の上方に設けられた半
田層とを含み、前記半田層が前記回路パターンに接して
配置されており、 前記Ni層は、前記回路パターンの少なくとも一部に接
触していることを特徴とする半導体装置。
2. An external circuit board having a circuit pattern, and a semiconductor element having an electrode electrically connected to the circuit pattern and having a surface having the electrode facing the external circuit board. A semiconductor device comprising: the electrode including a Ni layer and a solder layer provided above the Ni layer, wherein the solder layer is disposed in contact with the circuit pattern; A semiconductor device in contact with at least a part of a circuit pattern.
【請求項3】 請求項1又は2に記載の半導体装置にお
いて、 前記Ni層の厚みは、前記半田層の厚みよりも厚いこと
を特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein a thickness of the Ni layer is larger than a thickness of the solder layer.
【請求項4】 請求項1から3のいずれかに記載の半導
体装置において、 前記Ni層は、無電解メッキにより形成されてなること
を特徴とする半導体装置。
4. The semiconductor device according to claim 1, wherein said Ni layer is formed by electroless plating.
【請求項5】 請求項1から4に記載の半導体装置にお
いて、 前記電極は、前記半導体素子の表面に設けられた電極層
を含み、 前記Ni層は、前記電極層の表面に接して設けられるこ
とを特徴とする半導体装置。
5. The semiconductor device according to claim 1, wherein the electrode includes an electrode layer provided on a surface of the semiconductor element, and the Ni layer is provided in contact with a surface of the electrode layer. A semiconductor device characterized by the above-mentioned.
【請求項6】 請求項1から5のいずれかに記載の半導
体装置において、 前記電極は、前記半導体素子の表面に露出している部分
の全面が前記半田層で覆われていることを特徴とする半
導体装置。
6. The semiconductor device according to claim 1, wherein the entire surface of a portion of the electrode that is exposed on a surface of the semiconductor element is covered with the solder layer. Semiconductor device.
【請求項7】 Ni層と前記Ni層の上方に設けられた
半田層とを含む電極を有する半導体素子を、前記電極を
有する表面と回路パターンを有する外部回路基板とを対
向させて配置する工程と、 少なくとも前記回路パターンの側面に前記半田層を被着
させ、前記電極と前記回路パターンとを熱圧着して、前
記電極と前記回路パターンとを電気的に接続する工程
と、 を有することを特徴とする半導体装置の製造方法。
7. A step of arranging a semiconductor element having an electrode including a Ni layer and a solder layer provided above the Ni layer such that a surface having the electrode and an external circuit board having a circuit pattern are opposed to each other. And a step of attaching the solder layer to at least a side surface of the circuit pattern, thermocompression bonding the electrode and the circuit pattern, and electrically connecting the electrode and the circuit pattern. A method for manufacturing a semiconductor device.
【請求項8】 Ni層と前記Ni層の上方の半田層とを
含む電極を有する半導体素子を、前記電極を有する表面
と回路パターンを有する外部回路基板とを対向させて配
置する工程と、 前記電極と前記回路パターンとを熱圧着して、少なくと
も前記Ni層を前記回路パターンの少なくとも一部に接
触させて、前記電極と前記回路パターンとを電気的に接
続する工程と、 を有することを特徴とする半導体装置の製造方法。
8. A step of arranging a semiconductor element having an electrode including a Ni layer and a solder layer above the Ni layer with a surface having the electrode and an external circuit board having a circuit pattern facing each other; Thermocompression-bonding an electrode and the circuit pattern to bring at least the Ni layer into contact with at least a part of the circuit pattern to electrically connect the electrode and the circuit pattern. Manufacturing method of a semiconductor device.
【請求項9】 請求項7又は8に記載の半導体装置の製
造方法において、 さらに、前記半導体素子と前記外部回路基板とを対向さ
せて配置する工程の前に、前記半導体素子の表面に前記
半導体素子の前記電極を設ける工程を有し、 前記電極を設ける工程において、前記Ni層は無電解メ
ッキ法により形成され、前記半田層はディッピングによ
り形成されることを特徴とする半導体装置の製造方法。
9. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of arranging the semiconductor element on a surface of the semiconductor element before the step of disposing the semiconductor element and the external circuit board so as to face each other. A method for manufacturing a semiconductor device, comprising: providing the electrode of an element; wherein, in the step of providing the electrode, the Ni layer is formed by electroless plating, and the solder layer is formed by dipping.
【請求項10】 半導体素子の表面の電極層の上方にN
i層を設ける工程と、 半田浴に前記半導体素子を浸漬する工程と、 等速で前記半田浴から前記半導体素子を引き上げ、前記
Ni層の上方に前記Ni層よりも薄い前記半田層を設け
る工程と、 を有することを特徴とする半導体装置の製造方法。
10. An N layer above the electrode layer on the surface of the semiconductor element.
providing an i-layer; immersing the semiconductor element in a solder bath; pulling up the semiconductor element from the solder bath at a constant speed; and providing the solder layer thinner than the Ni layer above the Ni layer A method for manufacturing a semiconductor device, comprising:
【請求項11】 請求項10記載の半導体装置の製造方
法において、 前記Ni層の上方に前記半田層を設ける工程において、
前記半導体素子の前記電極が設けられた表面にNパー
ジした熱風を吹き付け、前記半導体素子の前記電極以外
に付着した半田を除去する工程を有することを特徴とす
る半導体装置の製造方法。
11. The method for manufacturing a semiconductor device according to claim 10, wherein in the step of providing the solder layer above the Ni layer,
The blowing hot air was N 2 purged in the electrodes are provided surface of a semiconductor device, a method of manufacturing a semiconductor device characterized by comprising a step of removing the solder adhering to other than the electrode of the semiconductor element.
JP26383492A 1992-10-01 1992-10-01 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3331635B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26383492A JP3331635B2 (en) 1992-10-01 1992-10-01 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26383492A JP3331635B2 (en) 1992-10-01 1992-10-01 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH06120226A JPH06120226A (en) 1994-04-28
JP3331635B2 true JP3331635B2 (en) 2002-10-07

Family

ID=17394876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26383492A Expired - Lifetime JP3331635B2 (en) 1992-10-01 1992-10-01 Semiconductor device and manufacturing method thereof

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Country Link
JP (1) JP3331635B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3700598B2 (en) * 2001-03-21 2005-09-28 セイコーエプソン株式会社 Semiconductor chip, semiconductor device, circuit board, and electronic equipment
US9084377B2 (en) * 2007-03-30 2015-07-14 Stats Chippac Ltd. Integrated circuit package system with mounting features for clearance

Also Published As

Publication number Publication date
JPH06120226A (en) 1994-04-28

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