JPS5910063B2 - hand tai souchi no seizou houhou - Google Patents

hand tai souchi no seizou houhou

Info

Publication number
JPS5910063B2
JPS5910063B2 JP50036252A JP3625275A JPS5910063B2 JP S5910063 B2 JPS5910063 B2 JP S5910063B2 JP 50036252 A JP50036252 A JP 50036252A JP 3625275 A JP3625275 A JP 3625275A JP S5910063 B2 JPS5910063 B2 JP S5910063B2
Authority
JP
Japan
Prior art keywords
insulating layer
metal
layer
electrode
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50036252A
Other languages
Japanese (ja)
Other versions
JPS51111092A (en
Inventor
伸夫 佐々木
良育 東迎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP50036252A priority Critical patent/JPS5910063B2/en
Publication of JPS51111092A publication Critical patent/JPS51111092A/en
Publication of JPS5910063B2 publication Critical patent/JPS5910063B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、更に詳しくは半
導体基板とその絶縁層上の配線パターンとの接続を行な
う接続電極の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a connection electrode for connecting a semiconductor substrate and a wiring pattern on an insulating layer thereof.

半導体素子においてそのベース、エミッタ等の領域から
の電極引出しは、通常第1図に示すように行なわれる。
即ち半導体素子へのエミッタ拡散などの最終拡散工程終
了後、例えばP型であるベース領域1及び本例ではN+
型であるエミッタ領域2の全面に被着されているSiO
2の絶縁層3に、フォトエッチングでエミッタ電極用の
窓3aをあけ、これにアルミニウムなどの金属を全面蒸
着して電極引出し用の金属層4を形成する。次いで金属
層4をパターニングにして配線パターンを形成する。ベ
ース電極およびコレクタ電極等に対しても同様である。
ところで通常行なわれている蒸着方法により金属層4を
蒸着すると、絶縁層3の電極窓3a部分の周壁が切り立
つているので、金属層4は第2図に示す形状に被着し、
窓下端縁附近に厚みの薄い部分4aがしばしば発生し、
金属層4のパターニングのときこの部分が断線する恐れ
がある。
In a semiconductor device, electrodes are generally drawn out from regions such as a base and an emitter as shown in FIG.
That is, after finishing the final diffusion process such as emitter diffusion into the semiconductor element, the base region 1, which is, for example, P type, and in this example, N+
SiO is deposited on the entire surface of the emitter region 2 which is a mold.
A window 3a for an emitter electrode is formed in the insulating layer 3 of No. 2 by photo-etching, and a metal such as aluminum is deposited on the entire surface to form a metal layer 4 for leading out the electrode. Next, the metal layer 4 is patterned to form a wiring pattern. The same applies to the base electrode, collector electrode, etc.
By the way, when the metal layer 4 is deposited by a commonly used vapor deposition method, since the peripheral wall of the electrode window 3a portion of the insulating layer 3 is steep, the metal layer 4 is deposited in the shape shown in FIG.
A thin part 4a often occurs near the lower edge of the window,
When patterning the metal layer 4, there is a risk that this portion may be disconnected.

このような問題を改善するには電極窓にテーパを付して
摺鉢状にする、又は絶縁層として最初は導電体を被着し
、配線部を除いてこれを陽極酸化等により絶縁体化して
平坦な下地を作る等幾つかの方法が提案されている。本
発明もその一つの提案に係るものであつで特殊な工程を
必要とせず、比較的簡単な方法で断線を阻止しようとす
るものである。。一般に絶縁体中に金属粒子を導入する
とその濃度が所定値以上になるとき絶縁体は急速にその
金属の性質を帯び導電性を持つようになる。
To improve this problem, the electrode window may be tapered to make it mortar-shaped, or a conductor may be initially applied as an insulating layer, and this may be made into an insulator by anodic oxidation, etc., except for the wiring. Several methods have been proposed, such as creating a flat base using The present invention relates to one such proposal, and attempts to prevent wire breakage using a relatively simple method without requiring any special steps. . Generally, when metal particles are introduced into an insulator and their concentration exceeds a predetermined value, the insulator rapidly assumes the properties of the metal and becomes conductive.

本発明の接続電極形成方法はかかる現象を利用してなさ
れたもので、その特徴とするところは、半導体基板中に
形成された素子領域あるいは該半導体基板上に形成され
た配線層を覆つてシリコン酸化物の絶縁層を形成し、前
記素子領域あるいは配線層上の前記絶縁層の所望箇所に
選択的に金属を被着し、次いで熱処理を行ない該金属と
該絶縁層の固溶体を形成し、該絶縁層を局部的に導電性
とし、これを該絶縁層の表面に形成する配線パターンと
前記各領域あるいは配線層との間の接続電極としたこと
にある。以下図面の実施例を参照しながら本発明を詳細
に説明する。第3図〜第6図は本発明の接続電極の形成
方法を説明する図であり、これらの図において11はシ
リコン半導体基板、12は二酸化ケイ素(SiO2)の
絶縁層、13はアルミニウムAt、金Au、銀Ag、チ
タンTiなどの金属層である。
The method for forming a connection electrode of the present invention has been made by taking advantage of this phenomenon, and is characterized by the fact that silicon An insulating layer of oxide is formed, a metal is selectively deposited on desired parts of the insulating layer on the element region or the wiring layer, and then heat treatment is performed to form a solid solution of the metal and the insulating layer, The insulating layer is locally conductive and used as a connection electrode between the wiring pattern formed on the surface of the insulating layer and each of the regions or wiring layers. The present invention will be described in detail below with reference to embodiments of the drawings. 3 to 6 are diagrams explaining the method of forming a connection electrode according to the present invention. In these figures, 11 is a silicon semiconductor substrate, 12 is an insulating layer of silicon dioxide (SiO2), and 13 is an aluminum At, gold It is a metal layer of Au, silver Ag, titanium Ti, etc.

先ず第3図に示すように最終拡散工程を終了して電極配
線用の金属層を蒸着するばかりとなつたシリコン半導体
基板11の表面に熱酸化等の方法でSiO2の絶縁層1
2を形成し、更にその全面にアルミニウムなどの金属を
蒸着して金属層13を形成する。次にフオトエツチング
により、基板11のベース領域やエミツタ領域などにお
ける電極コンタクト部と対応した部分の金属層13Aを
残し、他の部分の金属層13を除去して第4図のように
する。こうして電極コンタクト部に対応する金属層13
Aを残したのち熱処理を行なうと、絶縁層12と金属層
13Aとは反応して金属層13Aの金属原子が絶縁層1
2中へ溶け込み、第5図に示すように金属−SiO2の
固溶体が形成される。こ乏れは導電性をもつので、接続
電極として利用できる。次いで絶縁層12および接続電
極14の全面に第6図に示すようにアルミニウムなどの
金属を蒸着して金属層15を形成し、これをパターニン
グして所定の配線層を形成する。これにより配線2層の
金属層15は接続電極14を介して半導体基板11の電
極コンタクト部と確実に電気的に接続される。また金属
層15は層12,14で形成される下地が平坦なので、
断線の恐れはない。金属原子の絶縁層12への導入は熱
処理により 3行なうが、この熱処理温度はAt,Au
で600℃以上、Agで400℃以上、Tiで550℃
以上の温度で30分程度加熱することにより行なう。金
属層13の厚さ(高さ)は絶縁層12と同じ厚さかもし
くはやや厚くして、これらの平面を平坦3.あるいは接
続電極14がやや突出した状態にする。このようにすれ
ば金属層15と接続電極14との電気的接続は確実に行
なわれる。一例を挙げると二酸化シリコン絶縁層12の
膜厚は0.3μmとし、金属層13は金(Au)を0.
3μmの厚さに蒸着して形成し、熱処理は1050℃で
20分、窒素(N,)ガス中で行なつた。その結果、表
面の金を除去して絶縁層の抵抗値を測定したところ、0
.05Ω−Cmの抵抗率が得られた。以上詳細に説明し
たように本発明ではシリコン酸化物の絶縁層上に選択的
に金属を被着し、次いで熱処理を行ない金属と該絶縁物
の固溶体を形成し、該絶縁層を局所的に導電化し、これ
を配線層と半導体基板の接続電極にした。
First, as shown in FIG. 3, an insulating layer 1 of SiO2 is formed by thermal oxidation or the like on the surface of a silicon semiconductor substrate 11 that has just completed the final diffusion process and is about to be deposited with a metal layer for electrode wiring.
A metal layer 13 is formed by depositing a metal such as aluminum on the entire surface thereof. Next, by photo-etching, the metal layer 13A in the base region, emitter region, etc. of the substrate 11 in the portions corresponding to the electrode contact portions is left, and the other portions of the metal layer 13 are removed, as shown in FIG. In this way, the metal layer 13 corresponding to the electrode contact portion
When heat treatment is performed after A remains, the insulating layer 12 and the metal layer 13A react, and the metal atoms of the metal layer 13A form the insulating layer 1.
2, and a solid solution of metal-SiO2 is formed as shown in FIG. Since this layer has conductivity, it can be used as a connection electrode. Next, as shown in FIG. 6, a metal such as aluminum is deposited over the entire surface of the insulating layer 12 and the connection electrode 14 to form a metal layer 15, and this is patterned to form a predetermined wiring layer. Thereby, the metal layer 15 of the second wiring layer is reliably electrically connected to the electrode contact portion of the semiconductor substrate 11 via the connection electrode 14. Furthermore, since the metal layer 15 has a flat base formed by the layers 12 and 14,
There is no fear of disconnection. The introduction of metal atoms into the insulating layer 12 is carried out by heat treatment three times, and the temperature of this heat treatment is At, Au.
600℃ or higher for Ag, 400℃ or higher for Ti, 550℃ for Ti
This is done by heating at the above temperature for about 30 minutes. The thickness (height) of the metal layer 13 is the same as or slightly thicker than the insulating layer 12, so that these planes are flat 3. Alternatively, the connection electrode 14 may be in a slightly protruding state. In this way, the electrical connection between the metal layer 15 and the connection electrode 14 is ensured. For example, the thickness of the silicon dioxide insulating layer 12 is 0.3 μm, and the metal layer 13 is made of gold (Au) with a thickness of 0.3 μm.
It was formed by vapor deposition to a thickness of 3 μm, and heat treatment was performed at 1050° C. for 20 minutes in nitrogen (N,) gas. As a result, when the gold on the surface was removed and the resistance value of the insulating layer was measured, it was found to be 0.
.. A resistivity of 0.05 Ω-Cm was obtained. As explained in detail above, in the present invention, a metal is selectively deposited on an insulating layer of silicon oxide, and then heat treatment is performed to form a solid solution of the metal and the insulator, thereby making the insulating layer locally conductive. This was used as a connection electrode between the wiring layer and the semiconductor substrate.

これにより断線する等の問題を生じることがなく確実に
電極引出しを行なうことができる。なお、以上の説明に
おいては半導体基板中の領域から電極を導出する場合に
ついて説明したが、本発明は第7図に示すような多層配
線構造の層間接続導体を形成する場合にも適用すること
ができる。
As a result, electrodes can be drawn out reliably without causing problems such as disconnection. In addition, although the above explanation has been made regarding the case where electrodes are led out from a region in a semiconductor substrate, the present invention can also be applied to the case where an interlayer connection conductor of a multilayer wiring structure as shown in FIG. 7 is formed. can.

この場合、下層の配線層16上に絶縁層17を被着し、
該絶縁層17の所望箇所に上記方法で選択的に金属を導
入して層間接続体18を形成する。しかる後、絶縁層1
7上に金属層を被着し、これを選択的に除去して層間接
続体18に接続された上層の配線層19を形成する。こ
の場合にも、下層の配線層と上層の配線層との接続箇所
における段差をなくして、断線等の生じない接続を行な
うことができる。
In this case, an insulating layer 17 is deposited on the lower wiring layer 16,
Interlayer connectors 18 are formed by selectively introducing metal into desired locations of the insulating layer 17 using the method described above. After that, insulating layer 1
A metal layer is deposited on 7 and selectively removed to form an upper wiring layer 19 connected to interlayer connector 18 . In this case as well, it is possible to eliminate the difference in level at the connection point between the lower wiring layer and the upper wiring layer, and to perform a connection that does not cause disconnection or the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は従来の半導体素子の電極部分の構造を
示す断面図、第3図〜第6図は本発明の接続電極の形成
方法を説明する断面図、第7図は本発明の他の実施例を
示す断面図である。 図において1,11は半導体基板、2,12,17は絶
縁層、14,18は接続電極である。
1 and 2 are cross-sectional views showing the structure of the electrode portion of a conventional semiconductor element, FIGS. 3 to 6 are cross-sectional views explaining the method of forming the connection electrode of the present invention, and FIG. 7 is the present invention. FIG. 3 is a sectional view showing another embodiment of the invention. In the figure, 1 and 11 are semiconductor substrates, 2, 12, and 17 are insulating layers, and 14 and 18 are connection electrodes.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板中に形成された素子領域あるいは該半導
体基板上に形成された配線層を覆つてシリコン酸化物の
絶縁層を形成し、前記素子領域あるいは配線層上の前記
絶縁層の所望箇所に選択的に金属を被着し、次いで熱処
理を行ない該金属と該絶縁層の固溶体を形成し、該絶縁
層を局部的に導電性とし、これを該絶縁層の表面に形成
する配線パターンと前記各領域あるいは配線層との間の
接続電極としたことを特徴とする半導体装置の製造方法
1. Form an insulating layer of silicon oxide to cover an element region formed in a semiconductor substrate or a wiring layer formed on the semiconductor substrate, and select a desired location of the insulating layer on the element region or wiring layer. a wiring pattern in which a metal is deposited on the surface of the insulating layer, a solid solution of the metal and the insulating layer is formed by heat treatment, the insulating layer is made locally conductive, and this is formed on the surface of the insulating layer; A method for manufacturing a semiconductor device, characterized in that the electrode is used as a connection electrode between a region or a wiring layer.
JP50036252A 1975-03-26 1975-03-26 hand tai souchi no seizou houhou Expired JPS5910063B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50036252A JPS5910063B2 (en) 1975-03-26 1975-03-26 hand tai souchi no seizou houhou

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50036252A JPS5910063B2 (en) 1975-03-26 1975-03-26 hand tai souchi no seizou houhou

Publications (2)

Publication Number Publication Date
JPS51111092A JPS51111092A (en) 1976-10-01
JPS5910063B2 true JPS5910063B2 (en) 1984-03-06

Family

ID=12464570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50036252A Expired JPS5910063B2 (en) 1975-03-26 1975-03-26 hand tai souchi no seizou houhou

Country Status (1)

Country Link
JP (1) JPS5910063B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222542A (en) * 1982-06-18 1983-12-24 Matsushita Electric Ind Co Ltd Semiconductor device and preparation thereof

Also Published As

Publication number Publication date
JPS51111092A (en) 1976-10-01

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