JPS58222542A - Semiconductor device and preparation thereof - Google Patents
Semiconductor device and preparation thereofInfo
- Publication number
- JPS58222542A JPS58222542A JP57105969A JP10596982A JPS58222542A JP S58222542 A JPS58222542 A JP S58222542A JP 57105969 A JP57105969 A JP 57105969A JP 10596982 A JP10596982 A JP 10596982A JP S58222542 A JPS58222542 A JP S58222542A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- protective film
- conductive layer
- protection film
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
本発明は、半導体素子と、この素子、′ｆ：外部環境か
ら遮断する保護膜、および半導体素子からと９出す外部
端子を有する半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a semiconductor element, this element, a protective film for shielding it from the external environment, and an external terminal extending from the semiconductor element.
近年、半導体素子用の保護膜に、プラズマ分解反応を利
用した非晶質窒化ケイ素（以下＆−８ｉＮと略″ｊ）、
非晶質炭化ケイ素（ａ−８ｉＣ）または非晶質酸化ケイ
素（ａ−８ｉＯ）等による薄膜が用いらｊＬるようにな
っている。In recent years, amorphous silicon nitride (hereinafter referred to as &-8iN), which utilizes plasma decomposition reaction, has been used as a protective film for semiconductor devices.
Thin films made of amorphous silicon carbide (a-8iC), amorphous silicon oxide (a-8iO), or the like are now being used.
第１図は、この種の保護膜を用いた従来の半導体装置を
示す。１は半導体素子または半導体素子ケ含む基板であ
り、この基板に接して外部端子用のリード線２またに金
属蒸着膜３ａ、 ３ｂ、 ３ｃ形成さ扛ている。４
ｒＩ保護膜である。リード線２ば保護膜形成前に基板へ
接続さγＬるので、保護膜４ケ形成させる場合、じや壕
になり、均一に保護膜全形成することが難しい。また金
属等導電物質の蒸着膜３ａ、３ｂ、３ｃ等によって外部
端子を取り出す場合は、保護膜４ケ形成後、端子取り出
し用の穴をあけるか、端子取り出し部分をよけて保護膜
全形成しなけｎばならない。前者の場合に、保護膜４に
穴をあける工程が増加する欠点があり、′−ｉ：た後者
の場合は、保護膜形成マスクが複雑ＶＣなり、さらに保
護膜自体の強度や素子と保護膜の密着強度等信頼性が低
下するという欠点が牟る。FIG. 1 shows a conventional semiconductor device using this type of protective film. Reference numeral 1 denotes a semiconductor element or a substrate containing the semiconductor element, and metal vapor deposition films 3a, 3b, 3c are formed on lead wires 2 for external terminals in contact with this substrate. 4
It is an rI protective film. Since the lead wire 2 is connected to the substrate before the protective film is formed, if four protective films are to be formed, it becomes difficult to uniformly form all the protective films because of the formation of grooves. In addition, when taking out external terminals using vapor-deposited films 3a, 3b, 3c, etc. of conductive materials such as metals, after forming the four protective films, either make a hole for taking out the terminals, or form the entire protective film by avoiding the terminal taking out part. There must be. In the former case, there is a disadvantage that the process of making holes in the protective film 4 is increased; The drawback is that reliability such as adhesion strength is reduced.
不発明は、上記に鑑み、保護膜は均一に形成可能で、外
部電極のと９出しは、保護膜に穴をあける必要のない半
導体装置ケ提供することを目的とする０
不発明は、半導体素子と、半導体素子を外部環境から遮
断する保護膜と、この保護膜中に貫通して拡散さｎ１半
導体素子と外部端子と全接続する導電層とを有すること
を特徴とする。In view of the above, an object of the invention is to provide a semiconductor device in which a protective film can be uniformly formed, and external electrodes do not need to be formed with holes in the protective film. The semiconductor device is characterized by having an element, a protective film that shields the semiconductor element from the external environment, and a conductive layer that is diffused through the protective film and fully connects the n1 semiconductor element and external terminals.
不発明による半導体装置を製造する方法としては、半導
体素子の外部端子と９出し位置に導電性物質を堆積させ
た後、保護膜を形成する方法と、半導体素子上に保護膜
を形成した後、導電性物質を保護中に貫通して拡散させ
る方法がある。A method of manufacturing a semiconductor device according to the invention includes a method of depositing a conductive material on the external terminals and 9-output positions of a semiconductor element, and then forming a protective film, and a method of forming a protective film on the semiconductor element, and then There is a method of penetrating and diffusing a conductive substance during protection.
以下、本発明を実施例によって詳しく説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.
第２図に、本発明による半導体装置の構成例を示す断面
図である。第２図において、１ｏは半導体素子または半
導体素子を含む基板、１１は半導体素子中の配線、１２
は保護膜１３中に貫通して拡散さｎた導電物質による導
電層である。１４は保護膜１３の表面に露出している導
電層１２と少ｌくとも一部接着１面が重なっており、外
部端子として用いらｎるリード線である。１５１Ｌ、１
５ｂに、保護膜１３の表面に露出している導電膜１２と
少なくとも一部接するように蒸着さｎた金属等の導電物
質である。導電物質１５ａ、１６ｔ）はそのまま外部取
り出し用電極用配線としてもよいし、半導体素子間の接
続に利用してもよい。FIG. 2 is a sectional view showing a configuration example of a semiconductor device according to the present invention. In FIG. 2, 1o is a semiconductor element or a substrate containing a semiconductor element, 11 is a wiring in the semiconductor element, and 12 is a substrate containing a semiconductor element.
is a conductive layer made of a conductive material that penetrates and diffuses into the protective film 13. Reference numeral 14 denotes a lead wire whose adhesive surface overlaps at least a portion of the conductive layer 12 exposed on the surface of the protective film 13 and is used as an external terminal. 151L, 1
A conductive material such as a metal is deposited on the conductive film 5b so as to be at least partially in contact with the conductive film 12 exposed on the surface of the protective film 13. The conductive materials 15a, 16t) may be used as wiring for external electrodes as they are, or may be used for connection between semiconductor elements.
本発明の特徴は、半導体素子１ｏの保護膜１３中に、膜
１３を貫通して存在する導電層１２である。しかもこの
導電層１２は導電物質が保護膜１３を形成する物質中に
混在してなるものである。A feature of the present invention is that the conductive layer 12 exists in the protective film 13 of the semiconductor element 1o, penetrating the film 13. Moreover, this conductive layer 12 is formed by a conductive material mixed in the material forming the protective film 13.
不発明による導電層１２によって、半導体素子１０から
発生した信号または、半導体素子に送る信号に８易に送
信することができる。The conductive layer 12 according to the invention can easily transmit signals generated from the semiconductor device 10 or signals sent to the semiconductor device.
次に、以上のように構成さｎる半導体装置の製造方法に
ついて、いくつかの実施例をもとに説明する。Next, a method for manufacturing a semiconductor device configured as described above will be described based on several embodiments.
実施例１
第３図に、本発明による製造方法の一実施例の工程を示
した図である。Example 1 FIG. 3 is a diagram showing the steps of an example of the manufacturing method according to the present invention.
まず、半導体素子２０上にその配線となる金属凍たに導
電体２１を堆積させ（ａ）、次いで、導電体２１を適当
にエツチングすることによって半導体素子２０上の配線
を完成させる中）。配線用導電体２１は例えば、Ｗ、
Ｔａ、 Ｎｂ、 Ｍｎ、 Ｎｉ、 Ｏｒ、 Ｍ
ｏ。First, a conductor 21 is deposited on a metal layer on the semiconductor element 20 to form the wiring ((a), and then the conductor 21 is appropriately etched to complete the wiring on the semiconductor element 20). The wiring conductor 21 is made of, for example, W,
Ta, Nb, Mn, Ni, Or, M
o.
ステンレス鋼、 ＩＴＯ，５ｎ０２等である。次に本
発明による保護膜中に混在させることによって導電層を
形成させる導電性物質２２（以下貫通導電体と略す。）
を堆積させ（０）、外部と９出し配線用の部分すなわち
、半導体素子上の外部端子部分のみを残してと９除く（
ｄ）。貫通導電体２２としては例えば、Ｐｔ、 Ｐｄ、
Ａｕ、 Ａｌ、 Ｇａ、 Ｉｎ、 Ｓｎ、 Ｐｂ、
Ｓｂ、Ｔｉ。Stainless steel, ITO, 5n02, etc. Next, a conductive substance 22 (hereinafter abbreviated as a through conductor) is mixed in the protective film according to the present invention to form a conductive layer.
Deposit (0), leave only the external and 9 output wiring parts, that is, the external terminal parts on the semiconductor element, and remove 9 (
d). Examples of the through conductor 22 include Pt, Pd,
Au, Al, Ga, In, Sn, Pb,
Sb, Ti.
Ｚｎ、 Ｃｕ、 Ａｇ、 Ｃｄ、等である。These include Zn, Cu, Ag, Cd, etc.
次に半導体素子用保護膜２３を堆積させる。本実施例で
は、グロー放電によって分解させたａ−８ｉＮ 、
ａ−８ｉＣ、ａ−８ｉＯｆ用いた。基板温度は１５０〜
５００℃であり、真空度０．１〜５Ｔｏｒｒとした。原
料ガスｔＨ１ａ−ｓｉＮｔｖ場合、ＳｉＨ４トＮ２また
はＮＨ３等窒素化合物との混合気体であり、ａ−５ｉＣ
ｊの場合に、ＳｉＨ４とＣＨ４等炭素化合物との混合気
体、ａ −ＳｉＯの場合は、ＳｉＨ４と０２またに酸素
化合物である。保護膜２３を堆積させている間に貫通導
電体２２は、保護膜２３中に混合し、第３図（ｅ）に示
すように、混合し合った領域は導電層２４となる。導電
層２４は、保護膜２３の表面にまで達しており、適当な
条件を選んでやｎば、導電層２４は、厚さが６０００八
〜１μｍ８度で、ノ＜イアスミ圧１ｖで、４０Ａ〜以上
の電流密度が得らｎる。Next, a semiconductor element protective film 23 is deposited. In this example, a-8iN decomposed by glow discharge,
a-8iC and a-8iOf were used. The substrate temperature is 150~
The temperature was 500° C., and the degree of vacuum was 0.1 to 5 Torr. In the case of raw material gas tH1a-siNtv, it is a mixed gas with nitrogen compounds such as SiH4 and N2 or NH3, and a-5iC
In the case of j, it is a mixed gas of SiH4 and a carbon compound such as CH4, and in the case of a-SiO, it is an oxygen compound between SiH4 and 02. During the deposition of the protective film 23, the through conductors 22 are mixed into the protective film 23, and the mixed region becomes a conductive layer 24, as shown in FIG. 3(e). The conductive layer 24 reaches the surface of the protective film 23, and if appropriate conditions are selected, the conductive layer 24 has a thickness of 6,000 to 1 μm, a thickness of 40 A to 1 μm, and an asymmetry pressure of 1 V. A current density higher than that can be obtained.
この後、第２図に示したように、外部取出し電極として
リード線１４を使用してもよいし、１５ａのように、導
電物質をさらに堆積させ、外部端子（図示せず）に接触
させてもよい。さらに１５ｂのように保護膜１３上に配
線をめぐらせてもよい。After this, as shown in FIG. 2, the lead wire 14 may be used as an external electrode, or a conductive material may be further deposited as shown in 15a and brought into contact with an external terminal (not shown). Good too. Furthermore, wiring may be routed over the protective film 13 as shown in 15b.
なお、保護膜２３の堆積条件によっては、貫通導電一体
２２が再現よく導電層２４を作らない場合がある。この
場合には、真空中ないしは還元雰囲気、′−！たは希ガ
ス等不活性気体を流しながら、熱処理を行うことによっ
て、保護膜２３の堆積条件等のバラツキを償うことがで
きる。Note that depending on the deposition conditions of the protective film 23, the through-hole conductive unit 22 may not form the conductive layer 24 with good reproducibility. In this case, in a vacuum or in a reducing atmosphere, ′-! By performing the heat treatment while flowing an inert gas such as a rare gas or a rare gas, variations in the deposition conditions of the protective film 23 can be compensated for.
実施例２
第４図は、本発明による別の実施例の工程を示す。まず
、半導体素子３ｏ上に配線３１を行い、前述した実施例
と同様な方法で、保護膜３２を形成する（２Ｌ）。次に
、適当なマスク３３を半導体素子２、。Example 2 FIG. 4 shows the steps of another example according to the invention. First, a wiring 31 is formed on the semiconductor element 3o, and a protective film 32 is formed in the same manner as in the embodiment described above (2L). Next, a suitable mask 33 is applied to the semiconductor element 2.
３０上の外部端子部にあわせ、ヒータ３４によって半導
体素子３０を加熱する（ｂ）。加熱温度は保護膜３２の
堆積温度程度でよい。加熱させた状態で貫通導電体３５
を堆積させると、本発明による導電層３６が形成さｎる
。不実施例による導電層３６は前記実施例１の導電層２
４と同程度の導電性を示す。The semiconductor element 30 is heated by the heater 34 in accordance with the external terminal portion on the semiconductor element 30 (b). The heating temperature may be approximately the deposition temperature of the protective film 32. Penetrating conductor 35 in heated state
Depositing , a conductive layer 36 according to the present invention is formed. The conductive layer 36 according to the non-example is the same as the conductive layer 2 of the first embodiment.
It shows the same conductivity as 4.
なお第４図（ｂ）において、常温で貫通導電体３５を堆
積させた後、ヒータ３４で半導体素子３０を加熱するこ
とによっても、不発明による導電体３６が形成さｎる〇
さらに第４図（ｂ）において、貫通導電体３５のイオン
を打ち込むことによっても本発明による導電層３６が形
成される。イオン打ち込みには、金属イオンを用いる。In addition, in FIG. 4(b), the conductor 36 according to the invention can also be formed by heating the semiconductor element 30 with the heater 34 after depositing the through conductor 35 at room temperature. In (b), the conductive layer 36 according to the present invention is also formed by implanting ions of the through conductor 35. Metal ions are used for ion implantation.
例えばＡｌイオンでは、加速電圧は約１０Ｋｅｖで、１
０１５Ｃ「２程度の打ち込み量とする。イオン打ち込み
中に半導体素子３ｏを加熱してもよいし、打ち込み後に
半導体素子３ｏを加熱しても本発明による導電層３６が
形成さする。For example, for Al ions, the acceleration voltage is about 10 Kev, and 1
015C "The implantation amount is about 2. The conductive layer 36 according to the present invention can be formed by heating the semiconductor element 3o during the ion implantation or by heating the semiconductor element 3o after the ion implantation.
以上のように、不発明に膜厚の均一な保護膜中に導電体
を貫通して拡散させることにより、素子の保護を確実に
行うことができる。さらに、この保護膜ＴＦ−よって素
子の歩留をも向上させることができる。As described above, elements can be reliably protected by inventively penetrating and diffusing the conductor into a protective film having a uniform thickness. Furthermore, this protective film TF- can also improve the yield of devices.
第１図は従来の保護膜と外部端子とを有する半導体装置
の縦断面図、第２図に本発明による半導体装置の構成例
を示す縦断面図、第３図は不発明の第１の実施例におけ
る製造方法の手順を示す工程断面図、第４図は本発明の
第２の実施例における製造方法の手順を示す工程断面図
である。
１．１０，２０，３０・・・・・・半導体素子または半
導体素子を含む基板、４． １３． ２３． ３２・・
・・・・半導体素子保護膜、１２，２４．３６・・・・
・・導電層、２．３Ｊ ３ｂ、３０，１４，１５Ｊ
１ ｓｂ−・・・・・外部端子。
代理人の氏名 弁理士 中 尾、敏 男 ほか１名第１
図
＃５３ 図
第４図
、９１FIG. 1 is a vertical cross-sectional view of a conventional semiconductor device having a protective film and external terminals, FIG. 2 is a vertical cross-sectional view showing a configuration example of a semiconductor device according to the present invention, and FIG. 3 is a first embodiment of the invention. FIG. 4 is a process cross-sectional view showing the steps of the manufacturing method in the second embodiment of the present invention. 1.10, 20, 30... a semiconductor element or a substrate containing a semiconductor element, 4. 13. 23. 32...
...Semiconductor element protective film, 12,24.36...
・・Conductive layer, 2.3J 3b, 30, 14, 15J
1 sb-...External terminal. Name of agent: Patent attorney Nakao, Toshio, and 1 other person 1st
Figure #53 Figure 4, 91
Claims (1)
る保護膜と、前記保護膜中に貫通して拡散さ扛、前記半
導体素子と外部端子とを接続する導電層とを具備した半
導体装置。 （２）半導体素子上に外部環境から遮断する保護膜全形
成する際、あらかじめ前記半導体素子の外部端子形成位
置に導電性物質を堆積させておくことにより、前記保護
膜形成中に前記導電性物質全貫通して拡散させることに
より、半導体素子と外部端子とを接続する導電層を設け
ること全特徴とする半導体装置の製造方法。 （３）前記保護膜形成後に熱処理する工程金有する特許
請求の範囲第２項記載の半導体装置の製造方法。 （４）半導体素子上に外部環境から遮断する保護膜を形
成した後、半導体素子の外部端子形成位置に導電性物質
を堆積させることにより、前記導電性物質を前記保護膜
中に貫通して拡散させ、前記半導体素子と外部端子とを
接続する導電層を形成することを特徴とする半導体装置
の製造方法。 （６）前記導電性物質の堆積時またに堆積後に熱処理す
る工程’？！する特許請求の範囲第４項記載の半導体装
置の製造方法。 （６）導電性物質の堆積がイオン打ち込みにより行わｎ
る特許請求の範囲第４項記載の半導体装置の製造方法。[Scope of Claims] (1) A semiconductor element, a protective film that shields the semiconductor element from the external environment, and a conductive layer that is diffused through the protective film and connects the semiconductor element and external terminals. A semiconductor device equipped with. (2) When forming the entire protective film for shielding from the external environment on the semiconductor element, by depositing a conductive substance in advance at the external terminal formation position of the semiconductor element, the conductive substance can be deposited during the formation of the protective film. 1. A method of manufacturing a semiconductor device, characterized in that a conductive layer is provided to connect a semiconductor element and an external terminal by completely penetrating and diffusing the conductive layer. (3) The method for manufacturing a semiconductor device according to claim 2, further comprising a step of heat treatment after forming the protective film. (4) After forming a protective film on the semiconductor element to block it from the external environment, a conductive substance is deposited at the external terminal formation position of the semiconductor element, and the conductive substance penetrates and diffuses into the protective film. and forming a conductive layer connecting the semiconductor element and an external terminal. (6) A process of heat treatment during or after deposition of the conductive material? ! A method for manufacturing a semiconductor device according to claim 4. (6) The conductive material is deposited by ion implantation.
A method for manufacturing a semiconductor device according to claim 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57105969A JPS58222542A (en) | 1982-06-18 | 1982-06-18 | Semiconductor device and preparation thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57105969A JPS58222542A (en) | 1982-06-18 | 1982-06-18 | Semiconductor device and preparation thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58222542A true JPS58222542A (en) | 1983-12-24 |
| JPH0122985B2 JPH0122985B2 (en) | 1989-04-28 |
Family
ID=14421602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57105969A Granted JPS58222542A (en) | 1982-06-18 | 1982-06-18 | Semiconductor device and preparation thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58222542A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023971A (en) * | 1973-07-03 | 1975-03-14 | ||
| JPS51111092A (en) * | 1975-03-26 | 1976-10-01 | Fujitsu Ltd | Semiconductor manufacturing process |
-
1982
- 1982-06-18 JP JP57105969A patent/JPS58222542A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5023971A (en) * | 1973-07-03 | 1975-03-14 | ||
| JPS51111092A (en) * | 1975-03-26 | 1976-10-01 | Fujitsu Ltd | Semiconductor manufacturing process |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0122985B2 (en) | 1989-04-28 |
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