JP3270985B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a nickel silicide layer is formed in contact with a silicon wafer. The present invention relates to a method for manufacturing a semiconductor device having improved satisfaction.

[0002]

2. Description of the Related Art Generally, a semiconductor device for processing a large current,
For example, in a power MOS transistor or the like, an electronic circuit is formed on the surface of a silicon wafer, and a metal electrode formed on the back surface is connected to a header as a fixing member made of metal by a solder melting method. .

The metal electrode is disclosed in, for example,
As described in JP-A-0991, it is composed of a plurality of metal layers, a layer that easily adheres to silicon, a layer that blocks the intrusion of solder, and a layer that easily wets the solder. As a layer that easily adheres to silicon, a metal layer made of a transition metal such as titanium (Ti), chromium (Cr), or vanadium (V) has been conventionally used. Conventionally, a nickel (Ni) thin film has been adopted as a layer for stopping solder, and a silver (Ag) layer or a gold (Au) layer has been conventionally adopted as a layer that easily wets with solder. Aluminum (A) is used for wiring on the silicon wafer surface.
l) Materials are employed.

[0004]

In the power MOS transistor and the like of the above-mentioned conventional example, it is required that the operating characteristic R _on , that is, the value of the on resistance be low. To meet this demand, realizing good ohmic connection between the silicon wafer and the metal electrode is an important factor.

However, in a power MOS transistor,
Due to its structure, the impurity concentration of the silicon wafer is low,
Usually, a Schottky connection is formed with the transition metal such as titanium. Therefore, the contact resistance value between the silicon wafer and the metal layer is generally increased.

As a countermeasure, there is a method of forming a metal silicide layer as an intermediate layer at an interface between silicon and a metal film. However, among the various films formed on the back surface of the silicon wafer, the heat resistance is the lowest, and the heat resistance temperature is 450 ° C.
The temperature at which the metal silicide layer is formed is desirably 450 ° C. or lower so as not to adversely affect the electric wiring made of an aluminum film having a maximum temperature. Nickel silicide is considered as a material for forming silicide at such a low temperature.

However, nickel silicide inhibits the silicide reaction depending on the wafer temperature when depositing a nickel film on the back surface of a silicon wafer, as shown in the graph of the relationship between the wafer temperature and the reaction rate during nickel deposition in FIG. Or a crack may occur in the unreacted nickel film.

Accordingly, an object of the present invention is to form a stable nickel silicide layer without hindering a silicide reaction between a silicon wafer and nickel, and to achieve good mechanical and electrical connection with a metal electrode. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[0009]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of:
Forming an oxide film in an element isolation region; and forming an element formation region
Forming an oxide film on the oxide film;
Forming a polycrystalline silicon film,
Patterning the polysilicon film and gate oxidation
Forming a film and a gate electrode; and forming the gate electrode
And an insulating film is formed on the region surrounding the gate electrode.
The insulating film is removed except for the insulating film on the side surface of
Forming a sidewall, and forming an n-type silicon substrate on the silicon substrate.
Ion implantation of impurities to form source and drain
Having a gate electrode, a source and a drain.
The substrate temperature is set to 100 to 300 on a silicon substrate to be
C. and depositing a nickel film, and the nickel film
At 300 to 450 ° C. in a nitrogen atmosphere
Heat treatment, the gate electrode, source and drain
Forming a nickel silicide layer on the substrate .

[0010] Preferably, the temperature of the silicon wafer when depositing the nickel film is 150 ° C to 280 ° C.
Is more desirable. Further, the heat treatment temperature for forming the nickel silicide layer is desirably 300 ° C. to 450 ° C.

[0011]

According to the above arrangement, the nickel film is formed on the gate electrode,
By setting the wafer temperature when depositing on the side wall, source and drain to 100 ° C. to 300 ° C., the gate
Since a dense nickel film can be formed on the electrode and the source / drain, when forming a nickel silicide layer by heat treatment, the silicide reaction proceeds without disturbing the reaction, and a stable nickel silicide with good adhesiveness Layers can be formed.

FIG. 5 shows the relationship between the wafer temperature when depositing a nickel film and the reaction rate of the silicide reaction. That is, (1) If the wafer is not sufficiently heated when depositing a nickel film, the structure of the formed nickel film becomes coarse, and the nickel film itself shrinks greatly during the heat treatment process for silicide formation. And generate large stress,
The progress of the silicide reaction is inhibited, and cracks occur on the film surface. Further, if the stress of the unreacted nickel film increases and becomes larger than the adhesive force between the silicide film and the nickel film, the electrode may be peeled off.

On the other hand, (2) the silicon wafer at the time of depositing the nickel film is heated to a temperature of 30 at which the nickel silicide layer is formed.
When the temperature is higher than 0 ° C., the silicide reaction proceeds simultaneously with the deposition of the nickel film, and the shrinkage in the nickel film occurs. Since an unstable silicide layer is formed at the interface, the adhesiveness deteriorates.

Therefore, as described above, the nickel film can be deposited densely and the silicide reaction does not occur.
By depositing a nickel film in a temperature range of 0 ° C. to 300 ° C., a silicide reaction is not hindered due to the reasons (1) and (2), and a stable nickel silicide layer is formed. Better mechanical and electrical connections between the two. Further, silicide can be formed more stably by controlling the wafer temperature to 150 ° C. to 280 ° C.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a power MOS according to an embodiment of the present invention.
FIG. 2 is an enlarged vertical cross-sectional view of a main part of the transistor, and FIG.
Is a front sectional view showing a power MOS transistor, and FIG. 4 is a plan view showing a power MOS transistor with a sealing resin removed.

As shown in FIGS. 3 and 4, the power MO
The S transistor 1 includes a pellet 11 in which a transistor circuit as an electronic circuit is built,
And a header 2 as a fixing member made of a metal adhered via a solder layer 12, and three inner leads 3, 3a arranged so as to face the pellets 11.
And outer leads 4, 4a integrally connected to the inner leads 3, 3a, respectively.

The two inner leads 3a are used for the pellet 1
1, aluminum wirings 28 and 29 electrically connected to a gate electrode 21 and a source 23, respectively, which will be described later.
1 (see FIG. 1), and the other one of the inner leads 3 is formed so as to be integrally continuous with the header 2. The pellet 11, a part of the header 2, the inner leads 3, 3a, and the wires 13 are sealed with a sealing resin 14.

Hereinafter, referring to FIG. 1 and FIG.
The pellet 11 in the S transistor 1 will be described in detail. The pellet 11 is constituted by a transistor circuit formed on the silicon substrate 20. A gate electrode 21 made of polysilicon is formed on a silicon substrate 20 via a gate oxide film 22. Inside the silicon substrate 20 corresponding to the outside of the gate electrode 21 in the silicon substrate 20, a source 23 as a semiconductor diffusion layer portion is formed, and a drain 24 is formed below the silicon substrate 20.

The silicon substrate 20 has a CVD (Chemical Vapor Depo) by a chemical vapor deposition method.
An insulating film 25 made of an oxide film or the like is formed so as to cover the gate electrode 21 and the source 23, and the insulating film 25 has a gate contact hole 2.
6 and a source contact hole 27 are formed so as to face the gate electrode 21 and the source 23 and penetrate therethrough. Further, aluminum is applied on the insulating film 25, the source 23, and the gate electrode 21 by an appropriate means such as sputter deposition, and aluminum wirings 28 and 29 are formed by lithography.

On the other hand, a metal electrode 32 for the drain 24 is formed on the back surface of the silicon substrate 20, and the metal electrode 32 is formed by a plurality of metal layers. These metal layers are composed of a nickel silicide layer 33, a metal layer 34 of titanium, a metal layer 35 of nickel, and a metal layer 36 of silver in this order from the silicon substrate 20 side.

Here, the metal layer 36 made of silver improves the solder wettability when the metal electrode 32 on the back surface of the pellet 11 is connected to the header 2 as a fixing member made of metal by a solder melting method. . Metal layer 3 made of titanium
Numeral 4 is for preventing silicon in the activated silicon substrate 20 from diffusing to the surface of the metal layer 36 made of silver and deteriorating solder wettability when nickel silicide is formed by heat treatment. Further, the metal layer 35 made of nickel formed between the metal layer 36 made of silver and the metal layer 34 made of titanium is a layer for preventing diffusion of solder.

Hereinafter, a method of forming the metal electrode 32 during the manufacturing process of the power MOS transistor 1 according to the above configuration will be described. (1) The silicon back surface is formed to be n-type using, for example, antimony (Sb) as an impurity. After a transistor circuit or the like is formed by a predetermined process, a metal electrode 32 is formed on the back surface of the silicon wafer 70 by the following process. It is formed by a process.

(2) First, the back surface of the silicon wafer 70 is ground and finished to a thickness of 400 μm.
The finished surface has a whetstone particle size of 4000 and a surface roughness of 0.4.
1 μm. (3) The back surface of the ground silicon wafer 70 is treated with a hydrofluoric acid: water solution of 1: 100 for 30 seconds to remove the silicon oxide film.

(4) Next, using a vacuum deposition apparatus capable of depositing three kinds of metal films of nickel, titanium and silver, first, as shown in FIG. 33a is formed at 400 nm by an electron beam evaporation method. At this time, the vapor deposition surface temperature on the back surface of the wafer 70 is 100 ° C. to 300 ° C.

(5) Next, as shown in FIG. 2, the titanium layer 34 has a thickness of 150 nm, the nickel layer 35 has a thickness of 400 nm, and the silver layer 36 has a thickness of 1.3 μm on the back surface of the silicon wafer 70.
They are sequentially deposited. Each titanium layer 34, nickel layer 3
5. The thickness of the silver layer 36 is not limited to the above thickness, and may be arbitrarily changed. Further, a gold layer may be formed instead of the silver layer 36. If the titanium layer 34 is made of a material that does not react with silicon during the nickel silicide reaction,
It is not particularly limited to titanium.

(6) Then, the silicon wafer 70 on which the plurality of metal layers are formed on the back surface as described above is taken out of the vacuum vessel, and then placed in a quartz tube heat treatment furnace in a nitrogen atmosphere at 420.degree. Heated for minutes. By this heat treatment, silicon of the silicon wafer 70 and nickel 33a (FIG. 2) of the metal layer 32 adjacent to the silicon wafer 70 are mutually diffused to form a nickel silicide layer 33 (FIG. 1).

Here, as shown in step (4), the temperature of the silicon wafer 70 when depositing the nickel film 33a on the back surface of the silicon wafer 70 is set to 100 ° C. to 300 ° C. Since the dense nickel film 33a can be formed on the back surface, when the nickel silicide layer 33 is formed by the heat treatment, the silicide reaction proceeds without disturbing the reaction, and the stable nickel silicide layer 33 is formed. Can be.

FIG. 5 shows the relationship between the temperature of the wafer 70 when depositing the nickel film 33a and the reaction rate of the silicide reaction for forming the nickel silicide 33. As shown in FIG. 5, when nickel is deposited at a wafer temperature of 20 ° C., the silicide reaction proceeds only about 40% even if the heat treatment is performed. Moreover, this value varies.
It is also known that the silicide reaction is inhibited when a nickel film is deposited at a temperature higher than 300 ° C. If the wafer temperature when depositing nickel is 100 ° C. or higher, the silicide reaction proceeds by 90% or more, and
At 50 ° C. or higher, the reaction proceeds 100%.
It is more desirable to heat above.

On the other hand, when the wafer temperature during nickel deposition is 30
Even when the temperature is higher than 0 ° C., the silicide reaction is inhibited, and at 350 ° C. or higher, the reaction rate is reduced to 40% or lower. In this case, the silicide reaction proceeds at the same time as the nickel layer is deposited, and shrinkage occurs in the nickel film. Therefore, the reaction does not proceed uniformly, and an unstable silicide layer is formed at the interface between nickel and silicon. Therefore, the adhesiveness is deteriorated.

The wafer temperature at the time of depositing the nickel film is 100 ° C.
By controlling the temperature to ３００300 ° C., a stable nickel silicide layer can be formed, thereby reducing the resistance between the silicon wafer and the electrode and improving the adhesion of the metal electrode to the silicon wafer. In addition,
In order for the silicide reaction to proceed 100%, it is more desirable to control the wafer temperature during nickel deposition to 150 ° C. to 280 ° C.

The nickel silicide layer 33 is
Since it can be formed by a heat treatment at 350 ° C. to 450 ° C., among the various films formed on the surface of the silicon substrate 20, the aluminum wirings 28 and 29 having the lowest heat resistance and having a heat resistant temperature of 450 ° C. or less And a soldering temperature of 250 ° C. to 340 when the pellet 11 is connected to the header 2 by a solder melting method.
It has the advantage of being unaffected by ° C.

According to the above-described method, the silicon wafer 70 on which the plurality of metal layers constituting the electrodes are formed on the back surface is cut into a plurality of pellets 11 and assembled into the header 2 as a fixing member made of metal of the power MOS transistor. . The pellet 11 and the header 2 are formed by forming the lowermost metal layer 36 made of silver of the electrode 32 formed on the back surface of the pellet 11 into a solder layer 12 formed by a solder melting method.
Is connected to the header 2.

In the above embodiment, an n-type power MOS transistor has been specifically described. However, the present invention is not limited to the above-described embodiment, and can be applied to a p-type power MOS transistor. Further, in the metal electrode forming step in the embodiment, in the metal film deposition step (5), instead of forming three layers of titanium, nickel and silver, only a metal layer made of silver or gold is formed. You may.

In this embodiment, since a stable nickel silicide layer can be formed on the back surface of the silicon wafer, there is an effect that the reliability of the power MOS transistor can be improved or the mass production yield can be improved.

In the above embodiment, the case where nickel silicide is formed on the back surface of the silicon wafer has been specifically described. Next, as another embodiment of the present invention, a case where nickel silicide is formed in a bonding portion of a silicon wafer or a gate electrode will be described with reference to the drawings.

FIGS. 6 to 8 are sectional views showing a part of the manufacturing process of a MOS type semiconductor device according to another embodiment of the present invention. In the step shown in FIG. 6, the p-type silicon substrate 20 is formed.
A field oxide film 40 is formed in the element isolation region by a known selective oxidation technique. Next, the silicon substrate 20
An oxide film is formed in the element formation region. Next, a polycrystalline silicon film is formed on the oxide film, and an impurity for lowering the resistance is added thereto. Next, the gate electrode 21 and the gate oxide film 22 are formed by patterning the polycrystalline silicon doped with the impurity and the oxide film.

Next, an insulating film such as a silicon oxide film is formed on the entire surface of the silicon substrate 20, the gate electrode 21, and the gate oxide film 22, and the anisotropic etching of the insulating film is performed. The side wall 41 is formed while leaving the insulating film only on the side surface of 21. Next, using the sidewall 41 and the gate electrode 21 as a mask, an n-type impurity is ion-implanted at a high concentration into the silicon substrate 20 to form a source 23 and a drain 24.

Next, in a step shown in FIG. 7, a nickel film 42 is formed on the gate electrode 21, the side wall 41, and the exposed surface of the silicon wafer obtained in the step shown in FIG. Here, the temperature of the silicon substrate 20 when forming the nickel film 42 is controlled to a predetermined temperature in the range of 100 ° C. to 300 ° C. The nickel film 42
The temperature of the silicon substrate 20 when forming
By setting the temperature to 0 ° C. or higher, a dense nickel film can be formed. By setting the temperature to 300 ° C. or lower, since a silicide reaction of nickel silicide does not occur, a stable and dense nickel film can be formed. it can.

Next, in the step shown in FIG. 8, the silicon substrate 20 on which the nickel film 42 obtained in the step shown in FIG. 7 is formed is heated in a nitrogen atmosphere at 400 ° C. for about 1 minute. By this heat treatment, the gate electrode 21,
A nickel silicide layer 33 is formed on the source 23 and the drain 24 in a self-aligned manner.

Here, as described in the step shown in FIG. 7, the temperature of the silicon substrate 20 at the time of forming the nickel film 42 on the entire surface of the gate electrode 21, the side wall 41, and the exposed rear surface of the silicon wafer is reduced. , 100 ° C ~
By controlling the temperature to a predetermined temperature in the range of 300 ° C., the dense nickel film 42 is formed, and a stable nickel silicide layer can be formed without inhibiting the reaction during the heat treatment.

It is more preferable to control the temperature to 150 ° C. to 280 ° C. so that the silicide reaction proceeds 100%. The nickel silicide layer reduces the electrical resistance at the junction and improves the adhesiveness. Thereafter, unreacted nickel is selectively removed. Thereafter, a desired process is performed to complete a MOS semiconductor device.

In this embodiment, since a stable nickel silicide layer can be formed on the surface of the silicon wafer, there is an effect that the reliability of the MOS type semiconductor device is improved or the yield of mass production is improved.

In the above description, the case where the invention made mainly according to the present invention is applied to a power MOS transistor which is the background of the application and the case where it is applied to another MOS type semiconductor device has been described. However, the present invention is not limited to these, as long as the semiconductor device is manufactured by a manufacturing method including a step of depositing a nickel film in contact with a silicon wafer and a step of forming a nickel silicide film by heat treatment. The present invention may be applied to a method for manufacturing a semiconductor device having another structure. The present invention can be applied to general semiconductor devices such as thyristors, large-capacity diodes, and power IC silicon devices.

Next, a film forming apparatus according to the present invention capable of controlling a wafer temperature when depositing a nickel film on a wafer within a range of 100 ° C. to 300 ° C. will be described with reference to the drawings. FIG. 9 shows a sputtering apparatus to which the present invention is applied. The sputtering apparatus of the present embodiment includes a wafer holder 51 supported by a holder support column 52 in a bell jar 50, and a silicon wafer 70 is set on the wafer holder 51, and the silicon wafer 70
The structure is such that a nickel target 53 is installed at a position opposed to.

Further, the wafer holder 51 is provided with a heating device 55 for heating the silicon wafer 70 so as to be in thermal contact therewith. The heating device 55 is connected to a temperature control device 57 by an electric wiring 56, and the heating temperature is controlled by the temperature control device 57 to 100 ° C. to 300 ° C.
Can be controlled. An exhaust pipe 5 for exhausting the gas in the bell jar 50 is provided in the bell jar 50.
4 are connected.

FIG. 10 shows an electron beam evaporation apparatus to which the present invention is applied. The electron beam evaporation apparatus according to the present embodiment includes a wafer holder 51 supported by a holder support column 52 in a bell jar 50.
1, a silicon wafer 70 is installed, and a nickel vapor deposition material 59 in a holder 58 is installed at a position facing the silicon wafer 70, so that an electron beam is generated by an electron beam source 60.

Further, the wafer holder 51 is provided with a heating device 55 for heating the silicon wafer 70 so as to be in thermal contact therewith. The heating device 55 is connected to a temperature control device 57 by an electric wiring 56, and the heating temperature is controlled by the temperature control device 57 to 100 ° C. to 300 ° C.
Can be controlled. An exhaust pipe 5 for exhausting the gas in the bell jar 50 is provided in the bell jar 50.
4 are connected.

Although the electron beam heating type vapor deposition apparatus has been described here, the present invention is not limited to this, and may be a resistance heating type vapor deposition apparatus. Further, FIGS. 9 and 10 show a case where one silicon wafer 70 is installed in the wafer holder 51, but the present invention is not limited to this, and a plurality of silicon wafers 70 may be installed. . Further, the heating device 55 for heating the silicon wafer is not limited to a heating method, and may be a resistance heating method or a heating method using a heated gas.

[0049]

According to the present invention, a nickel film is formed on a gate electrode.
Electrode, the sidewall, the source, the wafer temperature when depositing the drain, by a 100 ° C. to 300 ° C., gate
Since a dense nickel film can be formed on the gate electrode and the source / drain, when forming a nickel silicide layer by heat treatment, the silicide reaction proceeds without disturbing the reaction, and the nickel silicide with good adhesiveness Layers can be formed. For this reason, the mechanical and electrical connection with the electrode is improved, and there is an effect that the reliability of the semiconductor device manufactured by using this manufacturing method or the improvement of the mass production yield is achieved.

[Brief description of the drawings]

FIG. 1 is an enlarged vertical sectional view of a main part showing a power MOS transistor according to one embodiment of the present invention.

FIG. 2 is a longitudinal sectional view for explaining one step in the manufacturing method of the present embodiment.

FIG. 3 is a longitudinal sectional view showing a power MOS transistor according to one embodiment of the present invention.

FIG. 4 is a plan view showing a power MOS transistor according to an embodiment of the present invention, with a sealing resin removed.

FIG. 5 is a graph showing a relationship between a wafer temperature and a reaction rate during nickel deposition.

FIG. 6 is a cross-sectional view showing a part of a manufacturing process of a MOS semiconductor device according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view showing another part of the manufacturing process of the MOS type semiconductor device according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view showing yet another portion of the manufacturing process of the MOS semiconductor device according to another embodiment of the present invention.

FIG. 9 is a sectional view of a sputtering apparatus according to still another embodiment of the present invention.

FIG. 10 is a sectional view of an electron beam evaporation apparatus according to still another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 power MOS transistor 2 header 3, 3a inner lead 4, 4a outer lead 11 pellet 12 solder layer 13 wire 14 sealing resin 20 silicon substrate 21 gate electrode 22 gate oxide film 23 source 24 drain 25 insulating film 26 gate contact hole 27 Source contact holes 28, 29 Aluminum wiring 30 Gate contact part 31 Source contact part 32 Metal electrode 33 Nickel silicide layer 33a Nickel film 34 Metal layer made of titanium 35 Metal layer made of nickel 36 Metal layer made of silver 40 Field oxidation Film 41 side wall 42 nickel film 50 bell jar 51 wafer holder 52 holder support column 53 target 54 exhaust pipe 55 heating device 56 electric wiring 57 heating control device 5 Holder 59 Nickel vapor deposition material 60 electron beam generating device 70 silicon wafers

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Asao Nishimura 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Norio Ando 5-chome, Josuihoncho, Kodaira-shi, Tokyo 20-1 Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Yuji Fujii 5-2-1 Kamisumi Honcho, Kodaira City, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Masahiro Fujita, Kodaira City, Tokyo 5-20-1, Mizumotocho Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Yoshihisa Kobayashi 3-3-2 Fujihashi, Ome-shi, Tokyo Hitachi Tokyo Electronics Co., Ltd. (56) References JP-A-6-252091 (JP, A) JP-A-7-38104 (JP, A) JP-A-62-121916 (JP, A) JP-A-62-286236 (JP , A) JP-A-60-213058 (JP, A) JP-A-61-226922 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/28 301 H01L 21/336 H01L 29/78

Claims (4)

(57) [Claims] 1. A method of manufacturing a semi-conductor device, the step of forming the oxide film in the isolation region of the silicon substrate
When, to form a polycrystalline silicon film and forming an oxide film on the element forming region, an impurity on the oxide film
And that step, the oxide film and the polycrystalline silicon film is patterned
Forming a gate oxide film and a gate electrode, and forming an insulating film on the gate electrode and a region around the gate oxide film and the gate electrode.
And removing the insulating film except for the insulating film on the side surface of the gate electrode.
Forming a side wall by removing silicon, and ion-implanting an n-type impurity into the silicon substrate to form a source.
Forming a gate and a drain, and a silicon having the gate electrode, a source and a drain.
The substrate temperature is set at 100 to 300 ° C.
Depositing a nickel film on the substrate and depositing the nickel film on the substrate in a nitrogen atmosphere for 30 minutes.
Heat treatment at 0 to 450 ° C. to make the gate electrode and the source
Of forming nickel silicide layer on gate and drain
The method of manufacturing a semiconductor device characterized by having, when. 2. The method according to claim 1 , wherein the nickel film is deposited by a sputtering method or a vapor deposition method. 3. A semiconductor of the semiconductor device manufactured by the method according to claim 1 or 2. 4. A semiconductor device manufacturing apparatus for manufacturing a semiconductor device by the method for manufacturing a semiconductor according to claim 1 , 2 or 3 .