JP4700264B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device that operates at high speed and high power and a method for manufacturing the same.
[0002]
[Prior art]
  High-speed transistors operating in the microwave band and high-power transistors used for power conversion are applied in various fields including home appliances.
[0003]
  Semiconductor elements that constitute high-speed transistors and high-power transistors include bipolar transistors, thyristors, GTOs, IGBTs, and MOSFETs. These devices require high power to be turned on and off at high speed with a pulse signal, and a semiconductor substrate different from an integrated circuit substrate formed on a flat surface has been used for the purpose of achieving both power source withstand voltage and high speed. It was.
[0004]
  As shown in FIG. 13, the semiconductor substrate that has been used to constitute these elements is a low-concentration n-type semiconductor silicon that is a region for forming elements on a high-concentration n-type semiconductor silicon layer 1301 that is a substrate base. A two-layer substrate having a structure in which the layer 1302 is stacked (or a structure in which a low-concentration p-type semiconductor silicon layer is stacked on a high-concentration p-type semiconductor silicon layer in which the semiconductor conductivity is inverted) is used. Has been. A desired semiconductor device is formed by forming a semiconductor silicon layer having three or four layers of different impurity concentrations or conductivity types on the substrate using ion implantation technology, impurity diffusion technology, lithography technology, or the like. It was. The semiconductor element formed in this manner has a thick substrate in the element just manufactured because current flows from the back side to the front side (or the opposite direction) of the substrate.μmSince the thickness is ˜1 mm, the electric resistance of the substrate inserted in series with the element is large. Therefore, the back surface of the substrate is finally polished using the back surface polishing technology of the high impurity concentration silicon substrate which is the support substrate.μm~ 200μmThus, after reducing the substrate thickness of the element for the purpose of reducing the series electric resistance, a metal electrode was provided on the back surface to complete the semiconductor element.
[0005]
  The thickness of the back-polished semiconductor element is 200μmDegree. If it is made thinner than this, the mechanical strength is lowered and the element is broken.
[0006]
  Therefore, there has been a demand for a substrate having a thin semiconductor layer that does not have problems such as element breakage.
[0007]
  As described in Japanese Patent No. 3191972, as a technique for forming a structure having a thin silicon crystal layer on a metal substrate without using the back surface polishing method as described above, a porous structure is obtained by anodizing on a silicon single crystal substrate. A silicon layer is formed, and then a silicon single crystal is epitaxially grown at a temperature of about 950 ° C., and this is bonded to a metal substrate at a temperature of 800 ° C. Then, the silicon substrate is separated by the porous silicon layer, and thin There is a technology to create a metal substrate having a silicon layer, but since a high temperature of 800 ° C. or higher is used, there is a problem of diffusion of metal atoms into the semiconductor layer, and the impurity concentration profile when the epitaxial layer is multilayered in advance Control is extremely difficult, and since only a single-layer or two-layer semiconductor layer can be obtained, there is a problem that the manufacture of semiconductor elements cannot be simplified. It was.
[0008]
  The plane orientation of the semiconductor silicon crystal used in conventional semiconductor elements is such that MOSFETs and IGBTs have a low interface state density at the silicon / gate insulating film interface, and a high-quality oxide film with high withstand voltage can be obtained. Only {100} plane orientation.
[0009]
  Conventional vertical semiconductor elements have difficulty in forming n-type and p-type bipolar elements in the vertical direction. When forming semiconductor circuits such as inverters, individual semiconductor elements must be mounted on the wiring board. It was formed with.
[0010]
[Problems to be solved by the invention]
  Returning to the formation process of the semiconductor element, in order to form the semiconductor element, many processes such as impurity ion implantation and diffusion are necessary, and many of them require a heat process near 1000 ° C. Impurity distribution is difficult to control, and the yield decreases, causing a problem that the device price increases.
[0011]
  As the substrate plane orientation, the {100} plane could only be used from the viewpoint of manufacturing technology, resulting in a problem that the diffusion constant of electrons and holes was small and the current conduction or blocking speed of the device could not be increased. It was.
[0012]
  Furthermore, since the element is formed on the silicon substrate, the heat generated by the element is not easily released to the outside of the element, and the temperature of the element rises, resulting in an extreme increase in electrons or holes, and the element is thermally runaway. Or a complicated temperature compensation circuit is required.
[0013]
  Further, conventionally, since it has been difficult to form a plurality of vertical semiconductor elements on a single semiconductor substrate, there has been a problem that a semiconductor device formed using these semiconductor elements is enlarged.
[0014]
  The above-mentioned problem that the semiconductor device cannot be integrated and becomes large is caused by the problem that the wiring connecting adjacent semiconductor elements becomes long distance, thereby increasing the parasitic capacitance and inductance of the wiring and increasing the speed of the semiconductor device. The problem of being unable to do so has occurred.
[0015]
  The object of the present invention is to solve such problems, enable the introduction of a thin semiconductor layer that cannot be achieved by the prior art, reduce the series resistance of the substrate, increase the operating speed of the device, and manufacture the device. It is to make it possible to easily obtain a substrate whose impurity concentration profile has been controlled in advance and to reduce the manufacturing cost of the semiconductor element.
[0016]
  Furthermore, an object of the present invention is to form an element capable of conducting or interrupting current at high speed by using a {110} plane capable of obtaining a high electron diffusion constant and hole diffusion constant in the element. is there. Here, the {110} plane orientation refers to a plane orientation crystallographically equivalent to the (110) plane, for example, the plane orientation collectively referring to the (010) plane, the (001) plane, and the like.
[0017]
  Furthermore, in a semiconductor device formed using a plurality of the semiconductor elements, by forming the semiconductor elements on a single semiconductor substrate, the wiring connecting the elements can be shortened, and the parasitic capacitance of the wiring, Inductance is reduced, and the semiconductor device is driven at high speed.
[0018]
[Means for Solving the Problems]
  In order to solve the conventional problems of the present invention, the present invention provides a semiconductor substrate in which a semiconductor layer is formed on a substrate made of a metal substrate, the metal substrate comprising a metal substrate made of a first metal and A diffusion prevention layer for preventing the metal constituting the metal base from diffusing into the semiconductor layer, and a connection metal layer made of a second metal for electrically connecting the metal substrate and the semiconductor layer, The semiconductor layer is a silicon layer composed of one of a {110} plane orientation and a plane orientation equivalent to the plane orientation, and the semiconductor layer is composed of a plurality of semiconductor layers having different conductivity types. It is characterized by.
[0019]
  The semiconductor element of the present invention is characterized in that a bipolar transistor, a vertical MOSFET, and an IGBT are formed singly or in combination in a silicon crystal having a {110} plane orientation and an equivalent plane orientation. The vertical semiconductor element of the present invention is characterized in that a plurality of vertical semiconductor elements having different polarities are separated by an element isolation region and integrated on a single substrate.
[0020]
  Furthermore, the semiconductor element of the present invention is formed on a metal substrate, and the thickness of the semiconductor layer located immediately above the metal substrate is 20μmIt is characterized by the following. The method for forming a semiconductor substrate and a semiconductor element according to the present invention is a method for manufacturing a semiconductor substrate having a plurality of semiconductor layers having different conductivity types on a metal substrate, and the step of forming porous silicon on the silicon substrate A step of epitaxially growing a semiconductor layer having a plurality of conductivity types on the porous silicon, a step of bonding the epitaxial silicon layer and a metal substrate, and a step of bonding the metal substrate and the semiconductor substrate having the epitaxial silicon layer together And a step of separating the semiconductor substrate from the formed substrate at the interface between the epitaxial silicon layer and the porous silicon layer. Furthermore, in addition to the steps described above, the method for manufacturing a semiconductor element and a semiconductor substrate according to the present invention includes a step of forming a plurality of vertical semiconductor elements having different polarities on the same substrate, and electrically isolating the semiconductor elements. And a step of forming the element isolation region.
[0021]
  In addition, the method for forming a semiconductor substrate and a semiconductor element according to the present invention includes a step of forming the epitaxial silicon layer at a low temperature of 600 ° C. or lower.
[0022]
  According to the present invention, a semiconductor silicon layer having a controlled impurity concentration profile composed of crystals of {110} plane orientation is pre-laminated on a low-resistance metal substrate at a low temperature of about 600 ° C. or lower so that a semiconductor is formed on the metal substrate. Since the structure is formed with layers, the semiconductor layer can be thinned without the problem of substrate breakage in the backside polishing, which has been a problem in the past, so unnecessary parasitic resistance can be reduced and the device can be driven at high speed. Can be conventional 200μmThe thickness of the semiconductor layer was about 20μmBy reducing it to the following, the series resistance of the vertical semiconductor element can be reduced.
[0023]
  FIG. 12 is a plot of the cutoff frequency of the bipolar transistor against the substrate thickness. For each of the emitter, base, and collector layers, the conductivity type, substrate concentration, and thickness are each n-type 1 ×Ten ²⁰ cm ^-3 0.7μm; P type 5 ×Ten ¹⁸ cm ^-3 , 0.02μmAnd n-type 2 ×Ten ¹⁷ cm ^-3 , 0.5μmAnd n-type 1 × for the substrate in contact with the collector layerTen ²⁰ cm ^-3 It shows the dependency when The substrate needs to be as low resistance as possible to reduce the series resistance of the device, and the impurity concentration of the substrate is 1m, where the substrate resistivity is sufficiently lowΩ1x below about cmTen ²⁰ cm ^-3 A degree or more is required. Board thickness is 20μmThe cut-off frequency begins to deteriorate at a point exceeding 200, which is the conventional substrate thickness of 200μmThen, the cutoff frequency deteriorates to about half of the maximum value.
[0024]
  According to the invention, 20μmBy introducing the following substrate, the element can be driven at high speed. The above-mentioned n-type substrate is 1 × the opposite conductivity type p-type substrateTen ²⁰ cm ^-3 The same effect can be obtained even when the impurity concentration is about or higher. Furthermore, according to the present invention, the semiconductor silicon layer constituting the semiconductor layer uses a crystal having a {110} plane orientation parallel to the substrate surface, thereby increasing the diffusion constant of electrons or holes and increasing the current at high speed. Can be turned on or off. Further, by providing an element isolation region penetrating the semiconductor layer, a plurality of vertical semiconductor elements are formed on a single substrate, and further, wiring is formed on both sides of the semiconductor layer, thereby integrating the semiconductor elements. By reducing the size of the formed semiconductor device, it is possible to reduce the parasitic capacitance and inductance of the elements and wirings, thereby alleviating the problems of the element operation delay and the generation of surge voltage, which have been problems in the past. be able to.
[0025]
  Furthermore, according to the semiconductor substrate of the present invention, since the wiring layers can be formed on both surfaces of the vertical semiconductor layer, the inverter or ECL of the vertical semiconductor element that can only be obtained by mounting individual elements on the wiring substrate in the past. Since the (emitter coupling element) can be easily formed on a single substrate, various integrated circuits using vertical semiconductors can be realized.
[0026]
  The {110} plane orientation referred to in the present invention is a crystallographically equivalent plane orientation to the (110) plane. For example, the (011) plane, the (101) plane, etc. are generically named. Further, even if the orientation of the {110} plane does not necessarily coincide completely, the object of the present invention can be achieved almost equally, for example, (511) plane, (331) plane, (221) plane, (321) plane, A plane orientation close to the {110} plane orientation, such as the (531) plane, the (231) plane, the (351) plane, the (320) plane, or the (230) plane, may be used.
[0027]
  Furthermore, according to the semiconductor substrate of the present invention, since the semiconductor layer is formed on the metal substrate, the series resistance of the element that has been a problem in the conventional vertical semiconductor element can be sufficiently reduced. The current can be conducted or cut off at high speed. Further, since the thermal conductivity of the substrate is improved by using the metal substrate, heat generation of the element can be removed, and thermal runaway of the element due to the heat generation can be suppressed.
[0028]
  Furthermore, according to the semiconductor substrate of the present invention, as described above, a plurality of semiconductor layers having different conductivity types are formed in advance at a low temperature of about 600 ° C. or less, and the impurity profile can be precisely controlled. Since a steep impurity profile having a staircase shape between adjacent semiconductor layers can be obtained, a depletion layer region formed between semiconductor layers having different conductivity types can be minimized, and the base layer is thin. Alternatively, a high-performance element with a short channel length can be manufactured by a simple process.
[0029]
  The impurity concentration profile on the substantially staircase referred to in the present invention is that both adjacent semiconductor layers are formed by an epitaxial growth method at a low temperature of about 600 ° C. or less, and a steep concentration profile in which the diffusion of impurities is small at the junction interface. An impurity profile that cannot be obtained by the solid layer diffusion method or ion implantation method can be obtained.
[0030]
  The diffusion constant in silicon at 600 ° C for impurities such as As, P, B, and Sb present in silicon isTen ^-20 cm ² / s The diffusion distance defined by the square root of the product of the time in the atmosphere and the diffusion constant is 0.6 angstrom in 1 hour, and in the present invention, the low temperature of 600 ° C. or less is the diffusion of impurities in silicon. This refers to an area where no occurs.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
  (Example 1)
  A structure and manufacturing method of a semiconductor substrate according to Example 1 of the present invention will be described below with reference to FIG. In the following, the conductivity type refers to n-type and p-type semiconductors in silicon semiconductors, and a change in impurity concentration is also included in the difference in conductivity type. FIG. 1 shows a cross-sectional structure of a bipolar transistor substrate according to this embodiment. In FIG. 1, the bipolar transistor substrate includes an Si layer 101 having a first conductivity type for forming an emitter layer, and a first conductivity type as a second conductivity type for constituting a base layer. Si layer 102 having the opposite conductivity type, Si layer 103 having the third conductivity type for forming the collector layer, and a fourth conductivity type for forming the collector electrode contact region And a Si substrate having a fourth conductivity type, and a metal substrate forming a collector electrode and a bonding layer 107 bonding the semiconductor layer and the metal substrate.
[0032]
  The illustrated metal substrate 108 includes a base formed of a first metal (for example, Cu) and a connection metal layer formed of a second metal (for example, Ni) so as to cover the base. Yes.
[0033]
  In the bipolar transistor substrate of the present invention, a Si layer having a plurality of conductivity types is formed in advance on a metal substrate, and the Si layer 104 having the fourth conductivity type has an impurity concentration of 1 ×.Ten ²⁰ cm ^-3 More than about 20 thicknessμmTherefore, the series resistance of the formed element can be reduced, and an element that operates at high speed can be easily formed. Further, the Si layer is a Si single crystal having a {110} plane orientation, and has a large diffusion constant and can improve the operation speed as compared with a conventional substrate having a {100} plane orientation.
[0034]
  Further, since the Si layer is formed by low-temperature epitaxial growth at about 600 ° C. or less and the impurity profile is precisely controlled, a high-performance element can be easily manufactured. A method of manufacturing such a bipolar transistor substrate will be described with reference to FIG. FIG. 2 shows an npn-type bipolar transistor substrate as an example of a bipolar transistor according to the first embodiment, and shows a manufacturing method thereof. The bipolar transistor is formed as follows.
[0035]
  First, a porous silicon layer 202 is formed on a silicon substrate 201 having a {110} surface by using an anodizing method to become a substrate for epitaxial growth and then separate the silicon substrate and the silicon layer (FIG. 2 (a) ), This is treated in a hydrogen atmosphere at 1200 ° C. to seal the micropores on the surface. Epitaxial growth of n-type silicon 203 serving as an emitter layer is performed by sputtering at a temperature of 400 ° C. Next, using the same method, the p-type base layer 204, the n-type collector layer 205, and the n-type high concentration collector layer 206 are epitaxially grown in this order (FIG. 2 (b)). The thickness of each layer is 0.7μm, 0.02μm, 0.5μm, 0.1μmImpurity concentration is 1 ×Ten ²⁰ cm ^-3 , 5xTen ¹⁸ cm ^-3 , 2 ×Ten ¹⁷ cm ^-3 , 1xTen ²⁰ cm ^-3 It was. These values can be varied depending on the intended use of the device and the withstand voltage. However, the high-concentration collector layer 206 is desirably thin enough for the purpose of reducing resistance,μmThe following is desirable. This is a figure1220 as shownμmIn the case of a thick collector layer that is thicker than this, the electrical resistance of the collector electrode increases, so the collector charging time, which is defined by the product of this and the collector capacity, increases, and the cutoff frequency that indicates the operating speed decreases. is there.
[0036]
  Next, as shown in FIG. 2 (c), a metal substrate 208, which will be described later, which will be a support substrate for the element, and a silicon substrate described above are bonded. A Ni layer is formed on the bonding interface between the metal substrate and the silicon substrate, and a silicide layer 207 for bonding the metal substrate and the semiconductor layer is formed by a silicidation reaction at a temperature of about 500 ° C. or less by an RTA method or the like. Be joined.
[0037]
  The above metal substrate is formed as follows. First, a Cu substrate serving as a base for a metal substrate is prepared. The thickness of the Cu substrate does not cause a problem in mechanical strength.μmIt was. Subsequently, TaN is formed on the surface of the Cu substrate by, for example, an ordinary sputtering method in order to prevent diffusion of Cu into the silicon layer. The entire surface of the Cu substrate on which the TaN is sputtered is bonded to the surface of the metal substrate by passivation and silicidation with Si.400-500Ni is formed by plating at a low temperature of about ℃ or less. In this way, the metal substrate is formed.
[0038]
  The material for the base of the metal substrate is not limited to Cu, and the substrate resistance can be made sufficiently smaller than that of the high-concentration collector layer, such as Au and Ag.μΩAny conductive metal or metal compound having a resistivity of about cm or less may be used.
[0039]
  Further, the diffusion preventing layer is not limited to TaN, and any layer may be used as long as it can prevent diffusion of elements constituting the metal substrate into Si, such as TaSiN, TiN, TiSiN.
[0040]
  In addition, Ni of the connection metal layer that acts as a bonding material by silicidation is not limited to this, and any material that can cause a silicidation reaction with Si at a low temperature of about 500 ° C. or less, such as Ti, Co, and the like, can bond the substrates. good.
[0041]
  Next, separation is performed at the interface between the previously formed porous silicon 202 and the epitaxially grown silicon layer 203 (FIG. 2 (d)).
[0042]
  In this way, the semiconductor substrate according to the first embodiment is formed. By performing epitaxial growth at a low temperature of 600 ° C. or lower, there is no problem of impurity diffusion, which has been a problem in the past, so that the thickness and impurity concentration of each layer can be precisely controlled. In addition, since each functional layer can be formed by continuous sputter deposition, there is no need to use techniques such as impurity diffusion or ion implantation as in the prior art, and substrate formation that forms the basis for device formation is extremely simple and high quality. Is possible.
[0043]
  Next, a method for manufacturing a bipolar transistor using the above-described semiconductor substrate will be described with reference to FIG. First, a photoresist 307 for masking the emitter region is applied on the semiconductor substrate (FIG. 3 (a)) completed by the above-described process, and the resist is patterned by a stepper or the like, and the portion other than the portion that becomes the emitter region is applied. An opening is provided in the resist on the emitter layer (FIG. 3B).
[0044]
  Next, the emitter layer under the resist opening is removed by RIE or the like. Next, without removing the remaining photoresist, ions are implanted into the base layer 305 to form a base contact layer 308 for making electrical contact between the metal forming the base electrode and the silicon layer (FIG. 3). (C)). Since the resist is present in the emitter region, ion implantation is not performed. Next, as ionic speciesBF ₂ ⁺ Using the ion implantation technique used in semiconductor manufacturing, the impurity density of the base layer except directly under the emitter is 1 ×Ten ²⁰ cm ^-3 Then, ion implantation was performed, and recrystallization was performed by heat treatment in nitrogen at 550 ° C. for 1 hour. At a temperature of 550 ° C., recrystallization was possible without causing the problem of impurity diffusion.
[0045]
  After the above process, the photoresist 307 is peeled off, and an interlayer insulating film is formed on the entire surface of the substrate, for exampleSiO ₂  311 was deposited at a temperature of 400 ° C. by CVD. Interlayer insulation filmSiO ₂ The insulating material is not limited to SiON, SiOF, polyimide, PTFE and the like used in semiconductor manufacturing.
[0046]
  Thereafter, a photoresist for forming a contact hole is applied, the contact regions of the base and the emitter are patterned, and a contact hole is formed using the RIE method. Next, in order to prevent the spike of Al, which is an electrode material into Si, a base electrode 309 and an emitter electrode 310 were formed by depositing and patterning Al containing about 1% of Si in atomic composition by sputtering. (FIG. 3 (d)). For the above-described electrode, a low contact resistance may be achieved by using a salicide technique in which Co, Ni or the like is formed in advance by a sputtering method and self-aligned silicidation is performed using an RTA method.
[0047]
  In this manner, a bipolar transistor is produced using the substrate shown in the first embodiment. Since the ion implantation process is performed once and all the processes are performed at a low temperature of 600 ° C. or less, there is no problem of impurity diffusion. Therefore, a semiconductor substrate and a semiconductor element in which the impurity concentration of each functional layer is accurately controlled Easy to manufacture. Furthermore, the base layer is not an ion implantation method or an impurity diffusion method, but a low temperature epitaxial growth method of about 600 ° C. or lower is used, so that it can be easily formed thinly, and a high-performance semiconductor device can be easily produced at low cost. did it.
[0048]
  Furthermore, since the {110} plane having a large diffusion constant is used as the crystal plane orientation, a semiconductor device can be fabricated at a higher speed than conventional. High concentration collector layer is 0.2μmTherefore, the device characteristics are not deteriorated by the substrate resistance as in the prior art. The cutoff frequency indicating the high speed of the element was about 50 GHz in the conventional {100} plane silicon substrate device, whereas 116 GHz was obtained in this example.
[0049]
  (Example 2)
  The structure of the semiconductor substrate according to Example 2 of the present invention will be described with reference to FIG. FIG. 4 shows a vertical MOSFET substrate according to the second embodiment. A high-concentration drain layer 403 showing the first conductivity type on the metal substrate 401, and a second conductivity type having a different impurity concentration from the first conductivity type. The drain layer 404 and the third conductivity type opposite to the first conductivity type are shown, and the body layer 405 in which the channel of the MOSFET is formed is a method similar to the method shown in the first embodiment And formed on a silicon substrate having a {110} plane.
[0050]
  The conductivity type, impurity concentration and thickness of each layer are n-type 1 × for the high concentration drain layerTen ²⁰ cm ^-3 , 0.2μmN-type 2 × for drain layerTen ¹⁷ cm ^-3 , 0.5μm, Body type p-type 5 ×Ten ¹⁸ cm ^-3  0.2μmIt was. In the vertical MOSFET substrate in Example 2 of the present invention, a Si layer having a plurality of conductivity types is formed in advance on a metal substrate, and the Si layer 403 having the first conductivity type has an impurity concentration. 1xTen ²⁰ cm ^-3 More than about 20 thicknessμmTherefore, the series resistance of the formed element can be reduced, and an element that operates at high speed can be easily formed.
[0051]
  Further, the Si layer is a Si single crystal having a {110} plane orientation, and has a large diffusion constant and can improve the operation speed as compared with a conventional substrate having a {100} plane orientation. The Si layer is formed by low-temperature epitaxial growth at about 600 ° C. or lower and the impurity profile is precisely controlled, so that a high-performance element can be easily manufactured. A method of manufacturing a vertical MOSFET using such a vertical MOSFET substrate will be described with reference to FIG.
[0052]
  FIG. 5 shows a method of manufacturing a vertical n-channel MOSFET using the vertical MOSFET substrate according to the second embodiment, which will be described below.
[0053]
  First, to form the source region, ions that form a conductivity type opposite to the body regionAs ⁺ Are implanted by ion implantation to form a source region 506 (FIG. 5 (a)). Subsequently, a CVD method is used to form an interlayer insulating film.SiO ₂  507 to 0.5μmDeposited (FIG. 5 (b)). Thereby, the overlap capacitance between the gate electrode and the source region can be reduced.
[0054]
  Next, in order to form a gate electrode, a trench hole 508 is formed at a location to be the gate electrode (FIG. 5 (c)). This is done as follows. Photoresist is applied to the entire surface of the substrate, the photoresist is patterned, and an opening is provided in the resist of the trench creating portion. The opening is arranged in the source region. Next, a trench hole is formed by a commonly used RIE method. The bottom of the trench hole 508 is formed so as to reach the drain region 504, and in this embodiment, 0.8%.μm, Width 0.3μm, Length 20μmIt was. This value can be changed depending on the purpose of use of the element.
[0055]
  Next, after removing the photoresist, a gate oxide film is formed. The gate oxide film is formed with KrO ₂ Plasma oxidation was performed at a temperature of 400 ° C. using a mixed gas, and an oxide film having a thickness of 5 nm was formed on the inner wall of the trench hole. As a result, a high-quality oxide film having a breakdown voltage of 10 MV / cm or more can be uniformly formed on the inner wall of the trench hole 508 (FIG. 5 (d)).
[0056]
  Following the above, a gate electrode 510 is formed. For example, poly-Si as a gate electrode material is 0.1 at 400 ° C. by the CVD method.μmAfter the deposition, a film of Al containing about 1% of Si by atomic composition was formed by sputtering. Photoresist is applied to the entire surface of the substrate, and the gate electrode portion is patterned to complete the gate electrode.
[0057]
  Next, in order to form an interlayer insulating film, the entire surface of the substrate is formed at a temperature of 400 ° C. by the CVD method.SiO ₂ In order to form the source electrode, a photoresist is applied and the source electrode portion 509 is patterned. When patterning the source electrode 509, the photoresist opening is the sourcen ⁺ It is formed so as to straddle both the layer 506 and the p layer 505 of the body. By doing so, both the source potential and the body potential can be obtained at the source electrode.
[0058]
  Using the RIE method, the photoresist openingSiO ² Is etched to form a contact hole, and Al containing about 1% of Si in atomic composition is formed by sputtering to form a source electrode 509 (FIG. 5 (e)).
[0059]
  Through the above steps, a vertical MOSFET using the substrate according to Example 2 of the present invention is completed. It is not necessary to perform ion implantation for forming a body well as in the prior art, and the impurity concentration can be accurately controlled. Furthermore, since the functional layer necessary for element formation is already built in the substrate, the element manufacturing process can be simplified. Furthermore, the high concentration drain layer is 0.2μmAs a result, the series resistance of the device was low, and a vertical MOSFET with no deterioration in the speed performance of the device due to the substrate resistance was obtained as in the prior art.
[0060]
  Furthermore, for example, in the high concentration drain regionp ⁺  as well asn ⁺ The same effect can be obtained with a drain short-circuited element in which silicon is alternately arranged.
[0061]
  On the other hand, a vertical p-channel MOSFET in which the conductivity type of each layer is the opposite conductivity type can be manufactured by the same process. An example is shown below.
[0062]
  An embodiment in which the present invention is applied to a trench type vertical P-channel power MOS transistor will be described again with reference to FIG. In this case as well, a vertical P-channel MOSFET substrate having the structure shown in FIG. 4 can be used. The structure shown in FIG. 5A is a high-concentration drain layer 503 having a first conductivity type, and the conductivity type is the same as that of the drain layer 504 having the same impurity type but opposite to the first conductivity type. A body layer 505 having a second conductivity type and having a channel of a P-channel MOSFET is formed on a silicon substrate (not shown) having a (110) plane. The conductivity type, impurity concentration and thickness of each layer are p-type for the high concentration drain layer.Ten ²⁰ cm ^-3 , 0.2μmP-type 2 × for drain layerTen ¹⁷ cm ^-3 , 0.5μm, N-type 5 × for body layerTen ¹⁸ cm ^-3  0.2μmIt was. In this embodiment mode, the high concentration drain layer 503 has an impurity concentration of 1 ×.Ten ²⁰ cm ^-3 More than about 20 thicknessμmTherefore, the series resistance of the formed element can be reduced, and an element that operates at high speed can be easily formed. Further, the layer 503 is a Si single crystal having a (110) plane orientation, and has a large diffusion constant and can improve the operation speed as compared with the case of using a conventional (100) plane orientation substrate. The Si layer is formed by low-temperature epitaxial growth at about 600 ° C. or less, and the impurity profile is precisely controlled, so that a high-performance element can be easily manufactured.
[0063]
Specifically, the vertical trench structure P-channel MOSFET according to the present embodiment uses the substrate shown in FIG. 4 and, as shown in FIG. 5A, in order to form the source region, To introduce boron, which forms the opposite conductive form,BF ₂ ⁺ Is implanted by ion implantation to form a source region 506. Its impurity concentration is p-type 1 ×Ten ²⁰ cm ^-3 It is. Subsequently, a CVD method is used to form an interlayer insulating film.SiO ₂  507 to 0.5μmDeposited (FIG. 5B). Thereby, the overlap capacitance between the gate electrode and the source region can be reduced.
[0064]
  Next, as shown in FIG. 5C, in order to form a gate electrode, a trench hole 508 is formed at a location to be the gate electrode. This is done as follows. Photoresist is applied to the entire surface of the substrate, the photoresist is patterned, and an opening is provided in the resist of the trench creating portion. The opening is arranged in the source region. Next, a trench hole is formed by a commonly used RIE method. The bottom of the trench hole 508 is formed so as to reach the drain region 504. In this embodiment, the depth is 0.8.μm, Width 0.3μm, Length 20μmIt was. This value can be changed depending on the purpose of use of the element. Since the surface of the silicon 505 is the (110) plane, the inner wall surface of the trench hole 508 forming 90 ° with the silicon 505 surface is also the (110) plane.
[0065]
  Next, as shown in FIG. 5D, after removing the photoresist, a gate oxide film 511 is formed. The gate oxide film is formed with KrO ₂ Plasma oxidation was performed at a temperature of 400 ° C. using a gas mixed with a silicon oxide film having a thickness of 20 nm on the inner wall of the trench hole. As a result, a high-quality oxide film 511 having a withstand voltage of 4 to 5 MV / cm can be uniformly formed on the (110) plane inner wall of the trench hole 508. The withstand voltage between the gate and source of the P-channel MOS transistor having the gate oxide film 511 is 10V.
[0066]
  Next, as shown in FIG. 5E, a gate electrode 510 is formed. As a gate electrode material, for example, poly-Si is 0.1 at 400 ° C. by CVD.μmAfter the deposition, Al containing about 1% of Si by atomic composition was formed by sputtering. Photoresist is applied to the entire surface of the substrate and the gate electrode portion is patterned to complete the gate electrode 510.
[0067]
  Next, as shown in FIG. 5E, in order to form an interlayer insulating film 512, the entire surface of the substrate is formed at a temperature of 400 ° C. by the CVD method.SiO ₂ And a source electrode 509 is formed. The source electrode is formed by first applying a photoresist and patterning the opening for the source electrode portion 509. When patterning the source electrode opening, the photoresist opening is the sourcep ⁺ It is formed so as to straddle both the layer 506 and the n-layer 505 of the body.
[0068]
  By doing so, both the source potential and the body potential can be obtained at the source electrode 509. For the opening formation, the RIE method is used to form the photoresist opening.SiO ² The films 507 and 512 are etched to form contact holes, Al containing about 1% of Si in atomic composition is formed by sputtering, and this is patterned by etching to form the source electrode 509.
[0069]
  The trench structure vertical P-channel power MOS field effect transistor according to the present embodiment is completed through the above steps. The high concentration drain layer 503 is 0.2μmSince the resistance is sufficiently low, the series resistance of the element is low, and a high-speed transistor is obtained.
[0070]
  In the high concentration drain regionn ⁺  as well asp ⁺ The same effect can be obtained with a drain short-circuited element in which silicon is alternately arranged.
[0071]
  (Example 3)
  The structure of the semiconductor substrate according to Example 3 of the present invention will be described with reference to FIG. FIG. 6 shows a vertical IGBT substrate according to the third embodiment, which has an anode layer 603 having a first conductivity type on a metal substrate 601, and a second conductivity type opposite to the first conductivity type. Silicon having a {110} plane in the same manner as the method described in the first embodiment using the buffer layer 604, the conductivity modulation layer 605, and the third conductivity type gate layer 606 having the same polarity as the anode layer. It is formed on the substrate. In this example, the conductivity type, impurity concentration, and thickness of each layer are p-type 1 × for the anode layer.Ten ²⁰ cm ^-3 , 0.2μm, N-type 1 × for buffer layerTen ²⁰ cm ^-3 , 0.2μm, N-type 2 × conductivity modulation layerTen ¹⁷ cm ^-3  0.2μmP-type 5 × for gate layerTen ¹⁸ cm ^-3 , 0.2μmHowever, it can be changed depending on the use of the element and the withstand voltage. However, the anode layer 603 is desirably sufficiently thin for the purpose of reducing resistance,μmThe following is desirable. In the IGBT substrate in Example 3 of the present invention, a Si layer having a plurality of conductivity types is formed in advance on a metal substrate, and the Si layer 603 having the first conductivity type has an impurity concentration of 1 ×.Ten ²⁰ cm ^-3 More than about 20 thicknessμmTherefore, the series resistance of the formed element can be reduced, and an element that operates at high speed can be easily formed. Further, the Si layer is a Si single crystal having a {110} plane orientation, and has a large diffusion constant and can improve the operation speed as compared with a conventional substrate having a {100} plane orientation. The Si layer is formed by low-temperature epitaxial growth at about 600 ° C. or lower and the impurity profile is precisely controlled, so that a high-performance element can be easily manufactured. An IGBT manufacturing method using such an IGBT substrate will be described with reference to FIG.
[0072]
  FIG. 7 shows a method of forming an n-channel gate type IGBT element as an example on the semiconductor substrate described above, which is formed as follows.
[0073]
  First, the cathode region 707 is an ion for forming a conductivity type opposite to the gate layer.As ⁺ (FIG. 7 (a)). Subsequently, an interlayer insulating film is formed by CVD.SiO ²  708 to 0.5μmDeposited (FIG. 7 (b)). Thereby, the overlapping capacity of the gate electrode and the cathode region can be reduced.
[0074]
  Next, a trench hole 709 is formed at a location to be a gate electrode. Photoresist is applied to the entire surface of the substrate, patterning is performed, and an opening is provided in the resist in the trench creation portion. Next, a trench hole 709 is formed by a commonly used RIE method. The depth of the trench hole is formed so as to reach the conductivity modulation layer 705.μm, Width 0.3μm Length 20μm(FIG. 7 (c)). This value can be changed depending on the purpose of use of the element.
[0075]
  Next, after removing the photoresist, a gate oxide film is formed. The gate oxide film is formed with KrO ₂ Plasma oxidation was performed at a temperature of 400 ° C. using a plasma-excited plasma of a gas mixed with to form an oxide film having a thickness of 5 nm. As a result, a high-quality oxide film having a breakdown voltage of 10 MV / cm or more can be uniformly formed on the inner wall of the trench hole 709 (FIG. 7 (d)).
[0076]
  Following the above, a gate electrode 710 is formed. Poly-Si as the gate electrode material is 0.1 at 400 ° C by the CVD method.μmAfter the deposition, Al containing about 1% of Si by atomic composition was formed by sputtering. Photoresist is applied to the entire surface of the substrate, and the gate electrode portion is patterned to complete the gate electrode 710.
[0077]
  Next, in order to form an interlayer insulating film, the entire surface of the substrate is formed at a temperature of 400 ° C. by the CVD method.SiO ₂ In order to form a cathode electrode, a photoresist is applied and the source electrode portion 711 is patterned. When patterning the cathode electrode portion 711, the photoresist opening is the sourcen ⁺ It is formed to straddle both the layer and the p-layer of the body. In this way, both the source potential and the body potential can be taken by the cathode electrode. A contact hole is formed by etching SiO2 in the photoresist opening using the RIE method, and Al containing about 1% of Si by atomic composition is formed by sputtering to form a source electrode 711 (FIG. 7 (e )).
[0078]
  Through the above steps, a vertical IGBT using the substrate according to Example 3 of the present invention is completed. It is not necessary to perform ion implantation for well formation as in the prior art, and the impurity concentration can be accurately controlled. Since the functional layer necessary for the device is built in the substrate in advance, the device manufacturing process can be simplified. Furthermore, the anode layer is 0.2μmSince the resistance is sufficiently low, the series resistance of the element is small, and high-speed switching can be realized.
[0079]
  In addition, for example, in the anode regionp ⁺  as well asn ⁺ An equivalent effect can be obtained even with an anode short-circuited element in which silicon is alternately arranged.
[0080]
  Furthermore, the same effect can be obtained with p-channel IGBTs in which the conductivity type of each layer is the opposite conductivity type.
[0081]
  (Example 4)
  A semiconductor device according to Example 4 of the present invention will be described with reference to FIGS. The semiconductor device according to Example 4 is composed of complementary elements shown in FIG. FIG. 8 (a) shows a complementary inverter device using bipolar transistors. FIG. 8 (b) shows a complementary inverter device using a vertical MOSFET. FIG. 8 (c) shows a complementary inverter device using IGBT. Each semiconductor element that constitutes such an inverter device has a structure in which conduction types are reversed with each other, and since it is a vertical element, the element has a structure that penetrates the substrate from the front surface to the back surface, In the prior art, a plurality of elements having different polarities cannot be formed on the same semiconductor substrate. For this reason, since the elements created on different semiconductor substrates were manufactured by mounting them as individual elements, they could not be integrated, were large-sized, and the wiring connecting the constituent elements became longer, and the inductance Therefore, a problem such as generation of a surge voltage due to the inductance component has occurred. Furthermore, the conventional pnp bipolar transistor formed in the {100} plane orientation has a low operating speed due to a small diffusion constant of electrons and holes, and realizes a complementary device as shown in FIG. It was difficult to do.
[0082]
  The semiconductor device according to the fourth embodiment operates as an integrated circuit by forming wirings between the semiconductor elements on the semiconductor substrate by manufacturing each semiconductor element constituting the semiconductor device on a single semiconductor substrate. It was possible to do so. Since the semiconductor layer forming the semiconductor element uses silicon having {110} plane orientation, the diffusion constant of electrons and holes is large, and even if a pnp bipolar transistor is used, it has the same performance as an npn bipolar transistor. Therefore, a complementary configuration is possible, and a plurality of elements with reversed polarity can be mixed on a single semiconductor substrate, so that a semiconductor device such as an inverter can be miniaturized and the wiring between elements can be shortened. Therefore, the parasitic capacitance and parasitic inductance of the wiring can be reduced, problems such as operation delay and generation of surge voltage can be reduced, and a semiconductor device that operates at high speed can be provided at low cost.
[0083]
  Next, a method for forming a semiconductor device according to the fourth embodiment will be described with reference to FIG. FIG. 9 shows a complementary inverter device formed using npn-type and pnp-type bipolar transistors in the semiconductor device according to the fourth embodiment. The reference numerals in the figure correspond to those in FIG. An npn-type bipolar transistor 1021 and a pnp-type bipolar transistor 1022 are formed on a metal substrate 1015, and the elements are isolated in an element isolation region 1023. Both collector electrodes are electrically connected by a metal substrate, thereby realizing the circuit configuration shown in FIG. 8 (a). Since a structure in which a plurality of elements with different polarities are mixed can be formed on a single substrate, integration of vertical semiconductor elements, which could only be realized by mounting individual individual elements, is realized by the semiconductor substrate according to this embodiment. it can. Since the collector electrode is not connected to the external wiring as in the past, the parasitic capacitance and parasitic inductance associated with the wiring can be reduced, and the conventional problems such as operation delay and generation of surge voltage can be solved. It is possible to provide a semiconductor device.
[0084]
  A method for manufacturing such a semiconductor device in which a plurality of vertical semiconductor elements having different polarities are formed on a single substrate will be described with reference to FIG. FIG. 10 illustrates a manufacturing method of a complementary inverter using a bipolar transistor as an example.
[0085]
  First, as shown in FIG. 10 (a), a silicon substrate 1001 having a {110} plane orientation has a silicon epitaxial growth base on the surface, and a porous body for separating the base after bonding to a metal substrate. A quality silicon layer 1002 is formed by anodization. By treating this in a hydrogen atmosphere at 1200 ° C., the fine pores on the surface are sealed. Next, as a buffer layer for forming a semiconductor layer on the porous silicon surface, for example, n-type Si is added as Si having a conductivity type opposite to the first conductivity type of the first element to be formed later.μmThe buffer layer 1003 is obtained by epitaxial growth to some extent.
[0086]
  Next, as shown in FIG. 10 (b), as a silicon layer 1004 showing the first conductivity type for forming the emitter electrode of the first element, for example,p ⁺ Si is formed by sputtering, for example. In this example, 0.7μmThe film was formed with a film thickness of. Next, thep ⁺ As a protective layer on the surface of Si 1004, for example, by a CVD method at a temperature of 400 ° CSiO ₂  1005 is formed. Next, the photolithography method is used.SiO ₂ And thep ⁺ Patterning Si, thep ⁺ SiThe layer is etched until the buffer layer 1003 appears. Then remove the photoresist and only in the region where the first element existsp ⁺ The Si layer is left (FIG. 10 (b)). On this occasionSiO ₂ Layer 1005 is not removed.
[0087]
  Next, a silicon layer having a second conductivity type opposite to the first conductivity type of the second element is deposited on the etched surface. For example, using a sputtering method,n ⁺ Si is an example of the first conductivity type of the first elementp ⁺ Film is formed to have the same thickness as Si. Depositedn ⁺ Si is an epitaxial film 1006 that becomes the emitter electrode of the second element on the buffer film 1003, andp ⁺ On the oxide film on Si, it grows as amorphous silicon or polysilicon 1007 (FIG. 10 (c)).
[0088]
  Next, unwanted growth on the oxide filmn ⁺ Remove Si 1007. For the removal, for example, a mixed solution of iodic acid, hydrofluoric acid and acetic acid with little heat generation is used. Non-single crystal grown on oxiden ⁺ Si 1007 is an epitaxially grown single crystaln ⁺ Compared with Si 1006, the etching rate is faster and sufficient selectivity can be obtained.n ⁺ Non-single crystal without changing the film thickness of Si 1006n ⁺ Only Si 1007 can be removed. Next, using buffered hydrofluoric acid solutionp ⁺ By removing the oxide film formed on the Si surface, the structure shown in FIG. 10 (d) is completed.
[0089]
  Subsequently, a layer having a conductivity type opposite to the second conductivity type of the second element is formed as a layer 1008 indicating the third conductivity type serving as a base electrode of the second element, for example, by sputtering. To form. In this embodiment, 0.02 p-type Si is used.μmThe thickness was formed. Subsequently, SiO2 1005 is formed on the surface on which the p-type Si layer 1008 is deposited, for example, at a temperature of 400 ° C. by the CVD method. Patterning is performed by a photolithography method, and unnecessary oxide film and p-type Si other than the portion for forming the second element in the SiO2 1005 and the p-type Si layer 1008 are removed by, for example, the RIE method (FIG. 10 (e )).
[0090]
  Next, as a layer showing the fourth conductivity type forming the base electrode of the first element, a layer showing a conductivity type opposite to the first conductivity type of the first element is formed, for example, by sputtering. To form. In this example, n-type Si is 0.02μmThe thickness was formed. The deposited n-type Sip ⁺ It grows as an epitaxial film 1009 on the Si film 1004 and grows as amorphous silicon or polysilicon 1010 on the oxide film 1005 on the p-type Si layer 1008 (FIG. 10 (f)).
[0091]
  Subsequently, unnecessary p-type Si grown on the oxide film is removed. For the removal, a mixed solution of iodic acid, hydrofluoric acid and acetic acid with little heat generation is used. The non-single crystal p-type Si layer 1010 grown on the oxide film has a higher etching rate and a sufficient selection ratio compared to the epitaxially grown single crystal p-type Si layer 1009. Only the non-single crystal p-type Si layer 1010 can be removed without changing. Next, a buffered hydrofluoric acid solution is used to form the surface of the n-type Si layer 1008.SiO ₂  By removing 1005, as shown in FIG. 10 (g), a structure in which conductive types adjacent to each other in the semiconductor layer are inverted is completed.
[0092]
  By repeatedly using the above-described method, the remaining semiconductor layers, ie, the collector layer and the high-concentration collector layer are formed, and the structure shown in FIG. 10 (h) is obtained. The thickness of each layer is 0.5 for the collector layers of the first and second elements, respectively.μmFor the high concentration collector layer, 0.2μmIt was.
[0093]
  Next, as shown in FIG. 10 (i), the silicon substrate and the metal substrate 1015 are bonded together. For example, a TaN layer is formed on the surface of a Cu substrate, for example, by sputtering to prevent diffusion, and then a Ni layer is formed on the entire surface of the substrate by plating. The silicon substrate and the metal substrate are bonded to each other and processed at a temperature of 500 ° C. by an RTA method or the like, whereby Ni and Si cause a silicidation reaction to form a silicide layer 1024 to obtain a strong bond.
[0094]
  The material for the base of the metal substrate is not limited to Cu, and the substrate resistance can be made sufficiently smaller than that of the high-concentration collector layer, such as Au and Ag.μΩAny conductive metal or metal compound having a resistivity of about cm or less may be used.
[0095]
  Further, the diffusion preventing layer is not limited to TaN, and any layer may be used as long as it can prevent diffusion of elements constituting the metal substrate into Si, such as TaSiN, TiN, TiSiN.
[0096]
  Further, Ni as a bonding material by silicidation is not limited thereto, and any material may be used as long as it can cause a silicidation reaction with Si at a low temperature of about 400 to 500 ° C. or less, such as Ti and Co, and can bond substrates.
[0097]
  Subsequently, the bonded substrate is cut at the interface between the porous silicon portion 1002 and the buffer layer 1003, and the buffer layer is etched away by the RIE method to obtain the structure shown in FIG. 10 (j).
[0098]
  Next, in order to perform element separation between the first element and the second element, a photoresist is applied to the surface of the substrate opposite to the metal substrate, and the first element of the photoresist is formed by photolithography. An opening 1017 is provided on the boundary between the second element and the second element (FIG. 10 (k)). Next, a trench hole is formed in the opening by RIE. The bottom surface of the trench hole reaches the back surface from the surface of the semiconductor layer and reaches the surface of the silicide layer bonded to the metal substrate, thereby forming the structure shown in FIG. In order to remove the photoresist and then improve the interface properties between the isolation region and the semiconductor layer, Kr andO ₂ On the inner wall of the trench hole by plasma oxidation usingSiO ₂ Is formed to about 10 nm (FIG. 10 (m)). The oxide film only needs to have insulating properties, for example,NH _Three Formed using plasmaSi _Three N _Four It may be a membrane. Then inside the trench hole at a temperature of about 400 ° C by CVD methodSiO ₂  It fills with 1018 (FIG. 10 (n)). Formed by CVDSiO ₂ Need only be insulating, for exampleNH _Three WhenSiH _Four Formed usingSi _Three N _Four Etc. Substrate surfaceSiO ₂ For example, the structure shown in FIG. 10 (o) is obtained by removing the film by RIE. Thereby, the element separation of the first element and the second element was completed.
[0099]
  Next, a base electrode 1019 and an emitter electrode 1020 are formed by a method similar to the method described in Example 1, and the inverter device shown in FIG. 10 (p) is completed. The collector electrodes of the first element and the second element are connected by a metal substrate 1015, and no new wiring is required.
[0100]
  The complementary inverter device using bipolar transistors obtained in this way manufactures each semiconductor element that constitutes the inverter device on a single semiconductor substrate, so that wiring between the semiconductor elements is formed on the semiconductor substrate. And can be made to operate as an integrated circuit. Since the semiconductor layer forming the semiconductor element uses silicon having {110} plane orientation, the diffusion constant of electrons and holes is large, and even if a pnp bipolar transistor is used, it has the same performance as an npn bipolar transistor. Therefore, since it has a complementary configuration and a plurality of elements with reversed polarity are mixed on a single semiconductor substrate, it can be a small inverter device, and the wiring between the elements is shortened. Therefore, the parasitic capacitance and parasitic inductance of the wiring can be reduced, problems such as operation delay and generation of surge voltage can be reduced, and a semiconductor device that operates at high speed can be provided at low cost.
[0101]
  By applying the method shown in this embodiment, it is possible to form an integrated circuit with a common collector electrode, and a single semiconductor device such as an inverter using a vertical semiconductor element, which has been conventionally formed by combining individual elements. It can be efficiently integrated on a substrate to improve operation speed and reduce power consumption.
[0102]
  Since all the processes are performed at a low temperature of 500 ° C. or lower, there is no problem of impurity diffusion between semiconductors having different conductivity types, so that it is possible to easily control the impurity concentration distribution which is important for the characteristics of the device.
[0103]
  In this embodiment, an example of a bipolar transistor is shown. However, if the method shown in this embodiment is used, there is no essential difference even if a vertical MOSFET, IGBT, or the like is used as a vertical semiconductor element, and these are combined. It is also possible to form the same substrate. Similarly, an integrated circuit configuration in which a horizontal semiconductor element and a vertical semiconductor element are integrated on a single substrate is also possible.
[0104]
  It is also possible to use it as an ECL (emitter coupling element) by bonding a metal substrate as a power supply substrate after forming a wiring layer on the collector side in advance before bonding the metal substrate. It is possible to realize.
[0105]
  (Example 5)
  Regarding the method for forming an integrated circuit using a vertical semiconductor in which wiring layers are formed on both sides of a semiconductor layer in Example 5, the method for forming a wiring layer on the metal substrate side of the semiconductor layer will be described with reference to FIG. .
[0106]
  First, using the method shown in Example 4, after obtaining a form immediately before bonding a metal substrate in a process of forming a plurality of vertical semiconductor elements on a single substrate, an interlayer insulating film and As an insulating film, for exampleSiO ₂  By forming 1106 at a temperature of about 400 ° C. by the CVD method, a structure in which an interlayer insulating film material is present on the surface of the semiconductor layer is obtained as shown in FIG. The semiconductor layer 1104 in FIG. 11 (a) shows an example in which a plurality of bipolar transistors are formed on a single substrate, but the layer structure shown in the drawing is used to obtain a vertical MOSFET or IGBT. Even if not, the essence of the present embodiment does not change.
[0107]
  Next, in order to carry out the collector electrode lead-out wiring, an opening is provided in the collector electrode portion of the bipolar transistor of the interlayer insulating film 1106 using a normal photolithography method as shown in FIG.
[0108]
  At this time, patterning is performed so as to leave the interlayer insulating film on the boundary between the first element and the second element. This is because the interlayer insulating film on the element boundary functions as an RIE etching stop layer when element isolation is performed by the method shown in Example 4 from the surface of the semiconductor substrate opposite to the metal substrate later. is there.
[0109]
  As a wiring metal, for example, Al containing about 1% of Si in atomic composition is formed by sputtering, and then the photoresist is patterned by photolithography to form a collector electrode 1107 using a technique such as RIE. After that, as the interlayer insulating film 1108, for exampleSiO ₂ Is formed at a temperature of 400 ° C. By repeatedly using this, the collector side wiring shown in FIG. 11 (c) is formed. In the interlayer insulating film 1108, a via 1109 for electrically connecting the collector electrode 1107 to the second and subsequent wiring layers and the metal substrate may be formed.
[0110]
  Next, in order to bond the metal substrate serving as the support substrate and the power supply substrate to the semiconductor substrate formed as described above, the collector side surface of the semiconductor substrate, for example, the entire surfacen ⁺ Si 1110 is deposited by about 10 nm, for example, by sputtering. After thisn ⁺ A metal substrate 1111 is bonded to the Si layer. The metal substrate may be, for example, a substrate having a Ni surface as shown in Example 4, and the temperature is about 500 ° C. or less.n ⁺ A silicide layer 1112 is formed by a silicidation reaction between the Si layer and the Ni layer to obtain a strong bond (FIG. 11 (d)).
[0111]
  In this way, after forming the collector-side wiring, it is bonded to the metal substrate, and then the emitter-side wiring is formed by the method shown in Example 4, thereby providing a vertical semiconductor having wiring on both sides of the semiconductor layer. An integrated circuit using can be obtained.
[0112]
  Since a structure with wiring on both sides of a semiconductor layer containing multiple vertical semiconductors can be realized on a single substrate, ECL (emitter coupling elements) that require collector-side wiring can be easily formed on a single substrate. Is possible.
[0113]
【The invention's effect】
  According to the present invention, a semiconductor silicon layer having a controlled impurity concentration profile composed of crystals of {110} plane orientation is pre-laminated on a low-resistance metal substrate at a low temperature of about 600 ° C. or lower so that a semiconductor is formed on the metal substrate. Since the layer can be formed, there is no problem of substrate breakage in the backside polishing that has been a problem in the past, and the semiconductor layer can be thinned, so that unnecessary parasitic resistance can be reduced and the element can be driven at high speed. Conventional 200μmThe thickness of the semiconductor layer was about 20μmBy reducing it to the following, the series resistance of the vertical semiconductor element can be reduced. Furthermore, according to the present invention, the semiconductor silicon layer constituting the semiconductor layer is a crystal having a {110} plane orientation parallel to the substrate surface. It can be turned on or off. Furthermore, by providing an element isolation region for separating a plurality of semiconductor elements formed on a single substrate, by forming a plurality of vertical semiconductor elements on a single substrate, and further forming wiring on both sides of the semiconductor layer, By integrating the semiconductor element and thereby reducing the size of the formed semiconductor device, the parasitic capacitance and inductance of the element and the wiring can be reduced. Problems such as occurrence can be alleviated. Furthermore, according to the semiconductor substrate of the present invention, since the wiring layers can be formed on both surfaces of the vertical semiconductor layer, the inverter or ECL of the vertical semiconductor element that can only be obtained by mounting individual elements on the wiring substrate in the past. Since the (emitter coupling element) can be easily formed on a single substrate, various integrated circuits using vertical semiconductors can be realized.
[0114]
  Furthermore, according to the semiconductor substrate of the present invention, since the semiconductor layer is formed on the metal substrate, the series resistance of the element which has been a problem in the conventional vertical semiconductor element can be sufficiently reduced. The current can be conducted or cut off at high speed. Further, since the thermal conductivity of the substrate is improved by using the metal substrate, heat generation of the element can be removed, and thermal runaway of the element due to the heat generation can be suppressed. Furthermore, according to the semiconductor substrate of the present invention, a plurality of semiconductor layers having different conductivity types or impurity concentrations are formed in advance at a low temperature of about 600 ° C. or less, and the impurity profile can be precisely controlled. A high-performance device having a thin base layer or a short channel length can be manufactured by a simple process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a structure of a semiconductor substrate for a bipolar transistor according to Example 1 of the present invention.
FIGS. 2A to 2D are schematic views showing a method of manufacturing a semiconductor substrate for a bipolar transistor according to Example 1 of the present invention in the order of steps.
FIGS. 3A to 3D are cross-sectional views showing a method of manufacturing a bipolar transistor according to the present invention in the order of steps. FIGS.
FIG. 4 is a cross-sectional view showing the structure of a vertical MOSFET semiconductor substrate according to a second embodiment of the present invention.
FIGS. 5A to 5E are cross-sectional views showing a method of manufacturing a vertical MOSFET according to Embodiment 2 of the present invention in the order of steps.
FIG. 6 is a cross-sectional view showing the structure of an IGBT substrate according to Example 3 of the present invention.
FIGS. 7A to 7E are schematic views showing a method of manufacturing an IGBT according to Example 3 of the present invention in the order of steps.
FIG. 8 is a circuit diagram showing an example of a semiconductor device formed by manufacturing a vertical semiconductor element on a single substrate according to Example 4 of the present invention.
FIG. 9 is a cross-sectional view showing an example of a semiconductor device formed by manufacturing a vertical semiconductor element according to Example 4 of the present invention on a single substrate.
FIGS. 10A to 10P are schematic views showing, in the order of steps, a method for manufacturing a semiconductor device according to Example 4 of the present invention formed by manufacturing a vertical semiconductor element on a single substrate. FIGS.
FIGS. 11A to 11D are diagrams showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention formed by manufacturing vertical semiconductor elements on a single substrate. It is a schematic diagram which shows the method to form in order of a process.
FIG. 12 is a characteristic diagram showing the effect of improving the cutoff frequency indicating the operation speed of the device by reducing the series resistance of the device when the semiconductor layer thickness is reduced in the present invention.
FIG. 13 is a cross-sectional view showing the structure of a conventional silicon epitaxial substrate.
[Explanation of symbols]
101 Si layer having the first conductivity type
102 Si layer having second conductivity type
103 Si layer having third conductivity type
104 Si layer having the fourth conductivity type
108 Metal substrate composed of metal base and connecting metal layer
107 Bonding layer

Claims (3)

A vertical semiconductor device in which a semiconductor layer is provided on a metal substrate including a metal substrate and at least a part of an element is formed on the semiconductor layer, and is formed as a bonding layer for bonding the metal substrate and the semiconductor layer. A silicide layer for bonding the metal substrate and the semiconductor layer, wherein the metal substrate includes the metal base made of a first metal Cu, and the first metal Cu constituting the metal base is the semiconductor A diffusion prevention layer made of TaN or TaSiN formed on the surface of the metal base to prevent diffusion into the layer, and the metal base and the semiconductor layer formed on the entire surface of the metal base on which the diffusion prevention layer is formed. And a connection metal layer made of a second metal Ni for electrically connecting to each other.   The semiconductor layer has {110} plane orientation and plane orientation equivalent to the plane orientation, {511} plane, {331} plane, {221} plane, {321} plane, {531} plane, {231} plane 2. A semiconductor according to claim 1, comprising a silicon crystal having a plane orientation selected from the group consisting of: {351} plane, {320} plane, {230} plane and plane orientation equivalent thereto. apparatus. The semiconductor device according to claim 1, wherein the semiconductor layer includes a plurality of layers having different conductivity types .

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