JPS58213510A - Amplifying circuit - Google Patents

Amplifying circuit

Info

Publication number
JPS58213510A
JPS58213510A JP9617782A JP9617782A JPS58213510A JP S58213510 A JPS58213510 A JP S58213510A JP 9617782 A JP9617782 A JP 9617782A JP 9617782 A JP9617782 A JP 9617782A JP S58213510 A JPS58213510 A JP S58213510A
Authority
JP
Japan
Prior art keywords
emitter
collector
resistor
transistor
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9617782A
Other languages
Japanese (ja)
Inventor
Shigeru Kawamura
茂 川村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP9617782A priority Critical patent/JPS58213510A/en
Publication of JPS58213510A publication Critical patent/JPS58213510A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain a low distortion amplifying circuit having no negative feedback of an open loop by composing an input circuit of an emitter earthing type amplification transistor (TR) having emittor resistance, coupling a load to the input circuit through a current mirror and connecting a resistor having a resistance value (n) times the emitter resistance in series to (n) forward diodes. CONSTITUTION:An input terminal 1 is connected to the base of an npn amplification transistor TR1 having high hFE, the emitter of the TR1 is earthed through an emitter resistor R1 and the collector of the TR1 is connected to the collector of a pnp TR2 which is one component of the current mirror. Although the collector of a TR3 has the same characteristics as that of the TR1, the collector is earthed through series connection consisting of (n) TR4-TRn+3 each of which is short-circuited between its collector and base and a resistor R2. The voltage taken out from an output terminal 3 is (n) times the voltage applied to the input terminal 1. Namely, the circuit shown in figure is an (n) times amplifier.

Description

【発明の詳細な説明】 本発明はトランジスタを用いた増幅回路に関する。[Detailed description of the invention] The present invention relates to an amplifier circuit using transistors.

ループの負帰還をかけるのが常であった。この方法には
確かに利点もあるが、%にオーディオ・77プにおいて
は、高音域における不安定性などの欠点が指摘されてい
る。
It was customary to apply negative feedback in the loop. Although this method certainly has advantages, it has been pointed out that it has drawbacks such as instability in the high frequency range, especially in audio 77p.

本発明の目的は、したがって、オープン譬ルーズの負帰
還を有しない、低歪の増幅回路を提供することである。
It is therefore an object of the invention to provide a low distortion amplifier circuit without open loose negative feedback.

上記目的を達成するために、本発明による増幅回路は、
入力回路がエミッタ抵抗を有するエミッタ接地型の増幅
トランジスタで、負荷がカレント・ミラーを介して上記
入力回路に結合された、上記エミッタ抵抗のn倍の抵抗
値を有する抵抗とnヶのノ険方向ダイオードの直列接続
であることす駿旨とする。
In order to achieve the above object, an amplifier circuit according to the present invention includes:
The input circuit is a common emitter type amplification transistor having an emitter resistor, and the load is coupled to the input circuit via a current mirror, and the resistor has a resistance value n times that of the emitter resistor, and the n number of diagonal directions. The idea is to connect diodes in series.

本発明の有利な実施の態様においては、上記順方向ダイ
オードは上記増幅トランジスタと同一の、ベース・コレ
クタ・ショート接続されたトランジスタである。上記工
きツタ抵抗は零であっても差支えない。この場合には上
記ダイオードと直列に以下に附図な紗照しながら、実施
例を用いて本発明を一層許しく説明するが、それらは例
示に過ぎず、本発明の枠な越えることなしにいろいろな
改良や変形があり得ることは勿論である。
In an advantageous embodiment of the invention, the forward diode is the same base-collector short-connected transistor as the amplification transistor. The above-mentioned vine resistance may be zero. In this case, the present invention will be explained in more detail with reference to the accompanying drawings below in series with the above-mentioned diode, but these are merely illustrative and there are various connections without going beyond the scope of the present invention. Of course, significant improvements and modifications are possible.

第1図は本発明による増幅回路の回路図である。FIG. 1 is a circuit diagram of an amplifier circuit according to the present invention.

入力端子lは高いhF!c ’に有するnpn型の増幅
トランジスタTr1のベースに接続され、そのトランジ
スタTrlのエミッタはエミッタ抵抗比1を通して接地
され、コレクタはカレント・ミラーを構成、している一
方のpnp型のトランジスタTr2のコレクタに接続さ
れている。トランジスタT r 2ベースとカレント・
ミラーを構成している他方のpnp型のトランジスタT
r3のペースはともにトランジスタT r 2のコレク
タに接続され、それらのトランジスタTr2およびT 
r 3のエミッタはともIl′c電源端子2から電流を
供給される。トランジスタTr3のコレクタは、トラン
ジスタTr1と同じ特性を有する、コレクタ・ペース・
ショート接続されたn個のトランジスタTr4.・・・
TrH+3および抵抗R2の直列接続を通して接地され
ている。出力はトランジスタTr3のコレクタに接続さ
れた出力端子3から取り出される。
Input terminal l has high hF! c', the emitter of the transistor Trl is grounded through an emitter resistance ratio of 1, and the collector of the pnp transistor Tr2 forms a current mirror. It is connected to the. Transistor T r 2 base and current
The other pnp transistor T forming the mirror
The paces of r3 are both connected to the collectors of transistors Tr2 and their transistors Tr2 and T
Both emitters of r3 are supplied with current from Il'c power supply terminal 2. The collector of the transistor Tr3 has the same characteristics as the transistor Tr1.
n short-connected transistors Tr4. ...
It is grounded through the series connection of TrH+3 and resistor R2. The output is taken out from the output terminal 3 connected to the collector of the transistor Tr3.

第1図に示す回路は以下のように動作する。トランジス
タTr2およびトランジスタTr3は同一特性を有し、
それらを流れる電流それぞれ】および1′は相等しい。
The circuit shown in FIG. 1 operates as follows. Transistor Tr2 and transistor Tr3 have the same characteristics,
The currents flowing through them respectively] and 1' are equal in phase.

一力、TrlとTr4.・・・T r n+3もまた同
じ特性を持っているので、それらのベース−エミッタ間
の電圧■Bll w ■BF!4 * ”” BF!y
l+3は同一である0これをVBKと書けば、入力端子
1に加えられる電圧vxnと出力端子3に表われる電圧
■。の間の関係はつぎのように表わされる。
Ichiriki, Trl and Tr4. ...Tr n+3 also has the same characteristics, so their base-emitter voltage ■Bll w ■BF! 4 * “” BF! y
l+3 is the same 0 If this is written as VBK, the voltage vxn applied to input terminal 1 and the voltage appearing at output terminal 3 are ■. The relationship between is expressed as follows.

VIN = VBIC+ R1x 1  =−(1)■
o −nVBB + R2X I’ ・・・ (2)I
 = 1’であるから、(2)式は Vo= nVBll、−1−R2I   ・−(25と
書ける。(1)式と両式から1を消去すればとなる。こ
こで、R2−nR1であれば、(3)式はV(、= n
VBll++ n (VIN’  VBE )”’nV
zn −(4)となり、出力端子3に現われる電圧は入
力端子1に加えられた電圧のn倍となる。すなわち、第
1図に示された回路はn倍の噌幅器を表わす。
VIN=VBIC+R1x 1=-(1)■
o -nVBB + R2X I'... (2) I
= 1', so equation (2) can be written as Vo = nVBll, -1-R2I ・-(25. If 1 is deleted from equation (1) and both equations, it becomes. Here, in R2-nR1 If so, equation (3) becomes V(, = n
VBll++ n (VIN'VBE)"'nV
zn - (4), and the voltage appearing at the output terminal 3 is n times the voltage applied to the input terminal 1. That is, the circuit shown in FIG. 1 represents an n-fold increaser.

以上の説明から明らかな通り、エミンタ抵抗几1は零で
あっても差支えない。このときには、勿論、抵抗比2も
また零である。
As is clear from the above explanation, the eminter resistor 1 may be zero. At this time, of course, the resistance ratio 2 is also zero.

以上説明した通り、本発明によれば、%に集積回路にお
いて、低歪の増幅回路がオーブン・ループ負帰還なしで
実現でき、高音域の安定性圧すぐれた低歪増幅回路が可
能となる。
As explained above, according to the present invention, a low distortion amplifier circuit can be realized in a highly integrated circuit without oven loop negative feedback, and a low distortion amplifier circuit with excellent stability in the high frequency range can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による増幅回路の回路図である。 1・・・入力端子、2・・・電源端子、3・−・出力端
子、Tr1#  Tr41 ”’ TI’n+3 ”’
 npn )ランジスタ、’rr2゜Ill r3・・
・pnp )ランジスタ、几1.■1.2・・・抵抗。 特許出願人  クラリオン株式会社 代理人 弁理士  永 1)武 三 部第1図
FIG. 1 is a circuit diagram of an amplifier circuit according to the present invention. 1... Input terminal, 2... Power supply terminal, 3... Output terminal, Tr1# Tr41 ``'TI'n+3'''
npn) transistor, 'rr2゜Ill r3...
・pnp) transistor, 1. ■1.2...Resistance. Patent Applicant Clarion Co., Ltd. Agent Patent Attorney Nagai 1) Takeshi Part 3 Figure 1

Claims (3)

【特許請求の範囲】[Claims] (1)入力回路がエミッタ抵抗を有するエミッタ接地型
の増幅トランジスタで、負荷がカレント・ミラーを介し
て上記入力回路に結合された、上記エミッタ抵抗のn倍
の抵抗値を有する抵抗とnヶの順方向ダイオードの直列
接続であることを特徴とする増幅回路。
(1) The input circuit is a common emitter type amplification transistor having an emitter resistor, and the load is a resistor having a resistance value n times the emitter resistor, which is coupled to the input circuit via a current mirror, and n number of resistors. An amplifier circuit characterized by a series connection of forward diodes.
(2)上記順方向ダイオードが上記増幅トランジスタと
同一のベース−コレクターショート接続されたトランジ
スタであることを特徴とする特許請求の範囲第1項記載
の増幅回路。
(2) The amplifier circuit according to claim 1, wherein the forward diode is the same base-collector short-connected transistor as the amplifier transistor.
(3)  上記エミッタ抵抗が零であることを特徴とす
る特許請求の範囲第1項記載の増幅回路。
(3) The amplifier circuit according to claim 1, wherein the emitter resistance is zero.
JP9617782A 1982-06-07 1982-06-07 Amplifying circuit Pending JPS58213510A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9617782A JPS58213510A (en) 1982-06-07 1982-06-07 Amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9617782A JPS58213510A (en) 1982-06-07 1982-06-07 Amplifying circuit

Publications (1)

Publication Number Publication Date
JPS58213510A true JPS58213510A (en) 1983-12-12

Family

ID=14158039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9617782A Pending JPS58213510A (en) 1982-06-07 1982-06-07 Amplifying circuit

Country Status (1)

Country Link
JP (1) JPS58213510A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4605907A (en) * 1985-05-20 1986-08-12 Teledyne Industries, Inc. Precisely adjustable voltage controlled current mirror amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199952A (en) * 1975-02-28 1976-09-03 Mitsubishi Electric Corp

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5199952A (en) * 1975-02-28 1976-09-03 Mitsubishi Electric Corp

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4605907A (en) * 1985-05-20 1986-08-12 Teledyne Industries, Inc. Precisely adjustable voltage controlled current mirror amplifier

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