JPS58212121A - Method of producing laminated ceramic condenser - Google Patents

Method of producing laminated ceramic condenser

Info

Publication number
JPS58212121A
JPS58212121A JP9553982A JP9553982A JPS58212121A JP S58212121 A JPS58212121 A JP S58212121A JP 9553982 A JP9553982 A JP 9553982A JP 9553982 A JP9553982 A JP 9553982A JP S58212121 A JPS58212121 A JP S58212121A
Authority
JP
Japan
Prior art keywords
ceramic
internal electrodes
chip
green
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9553982A
Other languages
Japanese (ja)
Other versions
JPH0145734B2 (en
Inventor
嶋田 勇三
好志 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Tokin Corp
Original Assignee
Tohoku Metal Industries Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tohoku Metal Industries Ltd, Nippon Electric Co Ltd filed Critical Tohoku Metal Industries Ltd
Priority to JP9553982A priority Critical patent/JPS58212121A/en
Publication of JPS58212121A publication Critical patent/JPS58212121A/en
Publication of JPH0145734B2 publication Critical patent/JPH0145734B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は積層セラミックコンデンサの製造工程における
積層方法に関するもめであ・る。
DETAILED DESCRIPTION OF THE INVENTION The present invention concerns a lamination method in the manufacturing process of a multilayer ceramic capacitor.

従来積層セラミックコンデンサの積層方法は、グリーン
シート法の場合、例えはドクターブレード法によりグリ
ーンセラミック膜を作製し該グリーンセラミック膜に内
部電極となる電極ペーストを印刷し、対向電極を形成す
るように複数枚積層し同時にその両性側に保饅の役割を
なすグリーンセラミック膜(内部電極ペーストの印刷さ
れ−ないもの)が配置され、積層される。スクリーン印
刷法の場合も構造上は同じでセラミック膜がスクリーン
印刷で形成される点が異なるだけである。いづれにしろ
こうして積層する場合、セラミック組成物の原料成分の
うちで蒸発しやすい成分があるとこれらの成分が焼成工
程で表面から蒸発し積層セラミックコンデンサチップの
表面に近い部分のセラミック組成物の組成比がチップ内
部と異なヂたものとなりチップの表面に近い位置にある
内部電極ではさまれたセラミック層の容量や絶縁抵抗が
低下するだけでな(、これらのセラミック層で絶縁破壊
を起し易くなり信頼性の低い積層セラミックコンデンサ
となってしまう欠点があった。
The conventional method for laminating multilayer ceramic capacitors is the green sheet method, for example, by creating a green ceramic film using a doctor blade method, printing an electrode paste that will become internal electrodes on the green ceramic film, and then stacking multiple layers to form counter electrodes. The sheets are laminated, and at the same time, a green ceramic film (without internal electrode paste printed thereon), which serves as an insulator, is placed on both sides and laminated. In the case of the screen printing method, the structure is the same, except that the ceramic film is formed by screen printing. In any case, when laminating layers in this way, if there are components that easily evaporate among the raw materials of the ceramic composition, these components will evaporate from the surface during the firing process, and the composition of the ceramic composition near the surface of the multilayer ceramic capacitor chip will change. The ratio is different from that inside the chip, which not only reduces the capacitance and insulation resistance of the ceramic layer sandwiched between the internal electrodes located close to the chip surface (but also makes it easy for dielectric breakdown to occur in these ceramic layers). This had the disadvantage of resulting in a monolithic ceramic capacitor with low reliability.

本発明の目的はこのような従来の欠点を除去せしめて積
層セラミックコンデンサチップ表面に近い位置にある内
部電極ではさまたセラミック層の容量、絶縁抵抗の低下
を抑制しチップ内部と同レベルの特性をもち、各セラミ
ック層間の特性が均一化した信頼性の高い積層セラミッ
クコンデンサの製造方法を提供するものである。本発明
は積層セラミックコンデンサの製造方法において、その
積層工程において内部電極ではさまれて積層される位置
にあるグリーンセラミック膜に比べ、セラミック組成物
の原料成分のうち蒸発−しやすい成分がより多く含まれ
ているグリーンセラミック膜を積層セラミックコンデン
サチップ中の複数のすべての内部電極のうちの両外側の
に位置する内部電極よりもさらにチップ表面に近い位置
に配置して積層、圧着することを特徴としている。
The purpose of the present invention is to eliminate such conventional drawbacks, suppress the decrease in the capacitance and insulation resistance of the ceramic layer, and achieve the same level of characteristics as the inside of the chip in the internal electrode located close to the surface of the multilayer ceramic capacitor chip. The present invention provides a method for manufacturing a highly reliable multilayer ceramic capacitor in which the characteristics between each ceramic layer are uniform. The present invention provides a method for manufacturing a multilayer ceramic capacitor, in which a green ceramic film that is sandwiched between internal electrodes and laminated in the lamination process contains more components that easily evaporate among the raw materials of the ceramic composition. The green ceramic film is placed closer to the chip surface than the inner electrodes located on both outer sides of all the plurality of internal electrodes in the multilayer ceramic capacitor chip, and is laminated and crimped. There is.

すなわち本発明は焼成過程において蒸発しやすい原料成
分をより多(含んだセラミック組成の膜を複数の内部電
極の両外側に積層付加させ、焼成中にチップ各部のセラ
ミック組成物の蒸発の不均一(チップ表面近(の方がチ
ップ内部より蒸発が活発に起こる。)により、蒸発しゃ
すいセラミック組成物の原料成分が蒸発したのち焼成後
のチップの表面近くと内部とのセラミック組成物の組成
比がほぼ均一になるように配慮したものである。
In other words, the present invention adds a ceramic composition film containing a larger amount of raw material components that easily evaporate during the firing process to both outer sides of a plurality of internal electrodes, thereby reducing uneven evaporation of the ceramic composition in each part of the chip during firing. After the raw material components of the ceramic composition that are less likely to evaporate evaporate near the chip surface (where evaporation occurs more actively than inside the chip), the composition ratio of the ceramic composition between the near surface and inside of the chip after firing is changed. Care has been taken to ensure that it is almost uniform.

以下実施例に従って詳細に説明する。第1図は本発明の
方法の方法によつて作製した積層セラミックコンデンサ
を示す模式的断面図である。pb(Fe 1/2 ・N
b 1/l ) 0.6? (Fs 2/s −wl/
a )0.3303で示される複合ペロプスカイト系誘
電体材料を予焼し、ボールミル粉砕したのちドクターグ
レード法により30μmのグリーンセラ4ツクシート2
を作製した。該グリーンセラミックシート上にスクリー
ン印刷法で内部電、テペース)(Ag−Pd系)を印刷
し電極層3.3′とする。それを積層しこの実施例では
61枚さらにその上下に電極層を印刷していないセラミ
ックシー)1を保護膜として積層する。(この実施例で
は10枚)ここで該セラミックシート1は焼成過程にお
いて蒸発しやすいナラミック組成物であるPbOを1.
0重量パーセント多く含んだセラミック組成の膜である
。次に熱プレス機で熱圧着し所定の形状に切断したのち
、脱バインダーおよび焼成及び外部電極形成を行なった
。得られた積層セラミックコンデンサチップの容量、絶
縁抵抗を責1定するとともに内部電極ではさまれた各セ
ラミック層のそれぞれの容量、絶縁抵抗も測定した。そ
の結果を表、及び第2図に示す。
A detailed explanation will be given below according to examples. FIG. 1 is a schematic cross-sectional view showing a multilayer ceramic capacitor manufactured by the method of the present invention. pb(Fe 1/2 ・N
b 1/l) 0.6? (Fs 2/s -wl/
a) A composite perovskite dielectric material shown by 0.3303 was pre-fired and ground in a ball mill, and then 30 μm Green Ceramic 4-sheet 2 was prepared using the doctor grade method.
was created. An internal electrode (TEPACE) (Ag-Pd type) is printed on the green ceramic sheet by a screen printing method to form an electrode layer 3.3'. In this example, 61 sheets of these are laminated, and ceramic sheets 1) having no electrode layer printed on top and bottom thereof are laminated as protective films. (10 sheets in this example) The ceramic sheet 1 contains 1.0% PbO, which is a naramic composition that easily evaporates during the firing process.
The membrane has a ceramic composition containing 0% by weight. Next, after thermocompression bonding with a hot press machine and cutting into a predetermined shape, binder removal, firing, and external electrode formation were performed. The capacitance and insulation resistance of the obtained multilayer ceramic capacitor chip were determined, and the capacitance and insulation resistance of each ceramic layer sandwiched between internal electrodes were also measured. The results are shown in the table and FIG.

表 比較の為に内部電極層の上下に各10枚のチップ内部の
グリーンセラミック膜と同一組成の印刷しないグリーン
セラミック膜を積層した従来の積層構造の生チップも同
時に焼成して同様に容量、絶縁抵抗を測定した。第2図
は積層セラミックコンデンサチップ中の内部電極ではさ
まれた上2122層にチップ表面に近い位置から番号を
付け、それぞれの場所での容量及び絶縁抵抗を測定し、
各セラミック層とその場所の容量抵抗積の関係を示した
図である。
For table comparison, raw chips with a conventional laminated structure in which 10 non-printed green ceramic films of the same composition as the green ceramic films inside the chip were laminated above and below the internal electrode layer were also fired at the same time to obtain similar capacitance and insulation. Resistance was measured. Figure 2 shows the upper 2122 layers sandwiched between internal electrodes in a multilayer ceramic capacitor chip, numbered from the position closest to the chip surface, and the capacitance and insulation resistance at each location measured.
FIG. 3 is a diagram showing the relationship between each ceramic layer and the capacitance-resistance product at that location.

表、第2図から明らかなように本発明による製造方法で
は従来のものに比べ内部電極ではさまれたセラミック層
の容量と絶縁抵抗の積が表面に近い部分でも全く低下せ
ず、全層にわたってはげフラットな値を示し全体的に従
来品エリも高レベルの値であり、またチップ全体の容量
と絶縁抵抗の積も従来品に比し鳥い値を示している。ま
た実施例ではPbOが1.0重−量チだけ多(含んだ場
合を示したが、種々の条件によってはPbO0量を5爪
量−程度まで増してもよい。
As is clear from the table and FIG. 2, in the manufacturing method according to the present invention, compared to the conventional method, the product of capacitance and insulation resistance of the ceramic layer sandwiched between internal electrodes does not decrease at all even in areas close to the surface, and throughout the entire layer. It shows a flat value and the conventional product has a high overall value, and the product of the capacitance and insulation resistance of the entire chip also shows a value that is higher than that of the conventional product. Further, in the embodiment, a case where PbO is included by 1.0 weight is shown, but depending on various conditions, the amount of PbO may be increased to about 5 weight.

以上述べたごと(本発明によれば積層セラミックコンデ
ンサの特性を飛躍的に向上させることが出来、信頼性の
^い積層セラミックコンデンサの製造方法の提供が可能
となった。
As stated above (according to the present invention, it is possible to dramatically improve the characteristics of a multilayer ceramic capacitor, and it has become possible to provide a method for manufacturing a highly reliable multilayer ceramic capacitor).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の積層構造を示す模式的断面図。 を歌専第2図は本発明品と従来品の積層セラミックコン
デンサチップ中の内部電極ではさまれた各セラミック層
の位置と容量抵抗積の関係を示す図。 た叡え。 図において 1は、セラミック組成物の原料成分のうち焼成過程にお
いて蒸発しやすい成分をより多(含んだセラミック膜で
あり、2は、所定のセラミック組成物のセラミック膜で
あり、3.3’は内部電極である。 〜      、      〜 (MΩ・〕 容 回置 一                        
      絶縁 滌抵 抗 ′iF
FIG. 1 is a schematic cross-sectional view showing the laminated structure of the present invention. Figure 2 shows the relationship between the position of each ceramic layer sandwiched between internal electrodes and the capacitance-resistance product in a multilayer ceramic capacitor chip of the present invention and a conventional product. Tae. In the figure, 1 is a ceramic film that contains a larger amount of components that easily evaporate during the firing process among the raw material components of the ceramic composition, 2 is a ceramic film of a predetermined ceramic composition, and 3. It is an internal electrode. ~ , ~ (MΩ・) capacity
Insulation resistance 'iF

Claims (1)

【特許請求の範囲】[Claims] グリーンセラミック膜と内部電極を交互に積層し、その
後圧着、焼成、外部電極形成を行なう積層セラミックコ
ンデンサの製造方法において、その積層をする際に用い
るグリーンセラミック膜を内部電極で社さまれて積層さ
れる位置に配置されるものと、複数の内部電極のうちの
両性側に位置する内部電極よりコンデンサ表面に÷←近
い位置に配置されるものの2種類に分けるとき前者のグ
リーンセラミック膜に比べ後者のグリーンセラミック膜
としてセラミック組成物の原料成分のうち焼成中に蒸発
しやすい成分がより多(含まれるグリーンセラミック膜
を用いることを特徴とする積層セラミックコンデンサの
製造方法。
In a manufacturing method for multilayer ceramic capacitors, in which green ceramic films and internal electrodes are alternately laminated, and then pressure bonded, fired, and external electrodes are formed, the green ceramic film used in the lamination is laminated with the internal electrodes. There are two types of green ceramic films: one is located at a position closer to the capacitor surface than the internal electrode located on both sides of multiple internal electrodes, and the other is located closer to the capacitor surface than the internal electrode located on both sides. A method for manufacturing a multilayer ceramic capacitor, characterized in that a green ceramic film is used that contains a larger amount of components that easily evaporate during firing among the raw material components of a ceramic composition.
JP9553982A 1982-06-03 1982-06-03 Method of producing laminated ceramic condenser Granted JPS58212121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9553982A JPS58212121A (en) 1982-06-03 1982-06-03 Method of producing laminated ceramic condenser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9553982A JPS58212121A (en) 1982-06-03 1982-06-03 Method of producing laminated ceramic condenser

Publications (2)

Publication Number Publication Date
JPS58212121A true JPS58212121A (en) 1983-12-09
JPH0145734B2 JPH0145734B2 (en) 1989-10-04

Family

ID=14140363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9553982A Granted JPS58212121A (en) 1982-06-03 1982-06-03 Method of producing laminated ceramic condenser

Country Status (1)

Country Link
JP (1) JPS58212121A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6058025B2 (en) * 2012-12-05 2017-01-11 吉田 健治 Control interface to facility management system

Also Published As

Publication number Publication date
JPH0145734B2 (en) 1989-10-04

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