JPH0515295B2 - - Google Patents
Info
- Publication number
- JPH0515295B2 JPH0515295B2 JP23161387A JP23161387A JPH0515295B2 JP H0515295 B2 JPH0515295 B2 JP H0515295B2 JP 23161387 A JP23161387 A JP 23161387A JP 23161387 A JP23161387 A JP 23161387A JP H0515295 B2 JPH0515295 B2 JP H0515295B2
- Authority
- JP
- Japan
- Prior art keywords
- multilayer ceramic
- raw
- ceramic capacitor
- internal electrode
- raw sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003985 ceramic capacitor Substances 0.000 claims description 17
- 239000000919 ceramic Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 238000007606 doctor blade method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000004898 kneading Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/008—Selection of materials
- H01G4/0085—Fried electrodes
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、積層セラミツクコンデンサ及びその
製造方法に関し、特に内部電極材料に特徴を有す
る積層セラミツクコンデンサに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same, and more particularly to a multilayer ceramic capacitor having characteristics in its internal electrode material.
一般に、従来の積層セラミツクコンデンサは第
５図乃至第８図の工程により形成される。まず、
第５図に示すように微細化したセラミツク粉末と
有機バインダを混練した後、ドクターブレード法
によつて生シートを作製する。次に、このシート
を所望の面積に切断し、その表面の片面にスクリ
ーン印刷により内部電極１２を被着・乾燥した生
シート１を用意する。次に内部電極１２を印刷し
た生シート１を、電極を印刷しない生シートから
なる保護層２で上下をはさむように、所望の枚数
を積み重ね、第６図に示すように積層体８を形成
し熱圧着した後、個片状態に切断して第７図ａ〜
ｃに示すような積層した生チツプ個片９を形成す
る。第７図ａ〜ｃにおいて、第７図ａは生チツプ
個片の斜視図、第７図ｂは第７図ａのｄ−d′断面
図、第７図ｃはｅ−e′断面図である。この生チツ
プ個片９を焼成し、両端に端子電極５を焼き付け
て第８図に示すような従来の積層セラミツクコン
デンサ２０を作製する。
Generally, conventional multilayer ceramic capacitors are formed by the steps shown in FIGS. 5 through 8. first,
As shown in FIG. 5, after kneading fine ceramic powder and an organic binder, a green sheet is produced by a doctor blade method. Next, this sheet is cut into a desired area, and an internal electrode 12 is adhered to one surface by screen printing and dried to prepare a raw sheet 1. Next, a desired number of green sheets 1 with internal electrodes 12 printed on them are stacked up and down with protective layers 2 made of green sheets without electrodes printed on them, to form a laminate 8 as shown in FIG. After thermocompression bonding, cut into individual pieces as shown in Figure 7a~
A laminated raw chip piece 9 as shown in c is formed. In Figures 7 a to c, Figure 7 a is a perspective view of an individual raw chip, Figure 7 b is a cross-sectional view taken along line d-d' in Figure 7 a, and Figure 7 c is a cross-sectional view taken along line ee'. be. This green chip piece 9 is fired, and terminal electrodes 5 are baked on both ends to produce a conventional multilayer ceramic capacitor 20 as shown in FIG.
上述した従来の積層セラミツクコンデンサ２０
は、内部電極にPdやAg−Pd合金を使用している
ので、その製造コストが高価になるという欠点が
ある。
The above-mentioned conventional multilayer ceramic capacitor 20
Since Pd or Ag - Pd alloy is used for the internal electrodes, the manufacturing cost is high.
また、内部電極を薄く印刷するので直列等価抵
抗（ESR）がその他の電解コンデンサに比べれ
ば小さいものの今後の高周波化を考えるならば、
まだまだ大きいという欠点がある。 Also, since the internal electrodes are printed thinly, the equivalent series resistance (ESR) is smaller than other electrolytic capacitors, but considering future high frequencies,
The drawback is that it is still large.
本発明の目的は、従来の積層セラミツクコンデ
ンサに比べ機械的強度が大きく、かつ安価に製造
することができ、また、直列等価抵抗を大幅に小
さくすることができる積層セラミツクコンデンサ
を提供することにある。 An object of the present invention is to provide a multilayer ceramic capacitor that has greater mechanical strength than conventional multilayer ceramic capacitors, can be manufactured at a lower cost, and can significantly reduce the equivalent series resistance. .
本発明の積層セラミツクコンデンサは、内部電
極パターンを設けた生シートを一枚以上積み重ね
た第１の生シート群と、前記第１の生シートの上
下に保護絶縁層のみからなる第２の生シート群を
積層した積層セラミツクコンデンサ素子において
その内部電極にセラミツク導電体｛Ba1-xYx｝
CuO3（０≦ｘ≦１）を用いたことを特徴として構
成される。
The multilayer ceramic capacitor of the present invention includes a first raw sheet group in which one or more raw sheets each having an internal electrode pattern are stacked, and a second raw sheet consisting of only protective insulating layers above and below the first raw sheet. A ceramic conductor {Ba 1-x Y
The structure is characterized by using CuO 3 (0≦x≦1).
本発明によれば、内部電極材料に｛Ba1-xYx｝
CuO3に代表される層状プロブスカイト構造を持
つセラミツク導電体を用いているので、安価で機
械的強度の大きい積層セラミツクコンデンサが得
られる。 According to the present invention, the internal electrode material contains {Ba 1-x Y x }
Since a ceramic conductor with a layered probskite structure such as CuO 3 is used, an inexpensive multilayer ceramic capacitor with high mechanical strength can be obtained.
また、近年層状プロブスカイト構造を持つセラ
ミツク導電体の「超伝導現象」が報告されている
が、この性質を用いることにより本発明の積層セ
ラミツクコンデンサは、直列等価抵抗を限りなく
小さくすることが可能である。 In addition, in recent years, the "superconducting phenomenon" of ceramic conductors with a layered provskite structure has been reported, and by using this property, the multilayer ceramic capacitor of the present invention can reduce the series equivalent resistance to an infinitesimal value. It is.
次に、本発明の実施例について図面を参照して
説明する。第１図乃至第４図は本発明の一実施例
の構造並びに製造方法を説明するために工程順に
示した斜視図並びに断面図である。
Next, embodiments of the present invention will be described with reference to the drawings. 1 to 4 are perspective views and cross-sectional views shown in order of steps to explain the structure and manufacturing method of one embodiment of the present invention.
まず、第１図に示すように、微細化した
BaTiO3のようなセラミツク粉末と有機バインダ
を混練した後、ドクターブレード法によつて生シ
ートを作製する。次にこの生シートを所望の面積
に切断し、その表面の片面にスクリーン印刷によ
り内部電極セラミツク導電体（Ba1-xYx）CuO3
（０≦ｘ≦１）を用いた１１を被着・乾燥した生
シート１を用意する。次に内部電極１１を印刷し
た生シート１を、電極を印刷しない生シートから
なる保護層２で上下をはさむように、所望の枚数
を積み重ねて、第２図に示すような積層体３を形
成し熱圧着する。 First, as shown in Figure 1, the
After kneading ceramic powder such as BaTiO 3 and an organic binder, a green sheet is produced by a doctor blade method. Next, this raw sheet is cut into a desired area, and an internal electrode ceramic conductor (Ba 1-x Y x ) CuO 3 is printed on one side of the raw sheet by screen printing.
(0≦x≦1) A green sheet 1 is prepared by applying and drying 11. Next, a desired number of raw sheets 1 with internal electrodes 11 printed thereon are sandwiched between upper and lower protective layers 2 made of raw sheets with no electrodes printed on them, to form a laminate 3 as shown in FIG. Then heat and press.
次に、第３図ａ〜ｃに示すように、個片状態に
切断して積層した生チツプ個片４を形成する。な
お、第３図ａは生チツプ個片の斜視図、第３図ｂ
は第３図ａのｂ−b′線の断面図、第３図ｃはｃ−
c′線の断面図である。 Next, as shown in FIGS. 3a to 3c, individual green chips 4 are formed by cutting into individual pieces and stacking them. In addition, Fig. 3a is a perspective view of an individual raw chip, and Fig. 3b is a perspective view of an individual raw chip.
is a sectional view taken along line b-b' in Fig. 3a, and Fig. 3c is a cross-sectional view taken along line b-b' in Fig. 3a.
It is a cross-sectional view taken along line c'.
次に、この生チツプ個片４を焼成し、両端に端
子電極５を焼き付けると本発明の積層セラミツク
コンデンサ１０が完成する。 Next, this raw chip piece 4 is fired and terminal electrodes 5 are baked on both ends to complete the multilayer ceramic capacitor 10 of the present invention.
以上説明したように、本発明積層セラミツクコ
ンデンサは、従来の積層セラミツクコンデンサと
比べて、内部電極に導電性セラミツクを用いてい
るので機械的強度も大きくかつ安価な製品を提供
が可能であり、また、層状プロブスカイト構造を
もつセラミツク導電体の「超伝導現象」を用いて
いるので第９図に示すように内部電極の臨界温度
以下において直列等価抵抗を限りなく小さくする
ことができる効果がある。
As explained above, compared to conventional multilayer ceramic capacitors, the multilayer ceramic capacitor of the present invention uses conductive ceramic for the internal electrodes, so it is possible to provide a product with greater mechanical strength and lower cost. Since this method uses the "superconducting phenomenon" of a ceramic conductor with a layered provskite structure, it has the effect of making the series equivalent resistance as small as possible below the critical temperature of the internal electrodes, as shown in FIG.
第１図乃至第４図は本発明の一実施例の構造並
びに製造方法を説明するために工程順に示した斜
視図並びに断面図であり、第１図は熱圧着時の積
層構造を示す分解斜視図、第２図は第１図の熱圧
着後の積層体のａ−a′線断面図、第３図ａ〜ｃは
第２図の破線で分離した生チツプ個片の斜視図と
そのｂ−b′線及びｃ−c′線の各断面図、第４図は
端子電極を形成した積層セラミツクコンデンサの
斜視図、第５図乃至第８図は従来の積層セラミツ
クコンデンサの構造並びにその製造方法を説明す
るために工程順に示した斜視図並びに断面図、第
９図は導電性セラミツクの直列等価抵抗と温度と
の関係を示す図である。
１……生シート、２……保護層、３，８……積
層体、４，９……生チツプ個片、５……端子電
極、１０，２０……積層セラミツクコンデンサ、
１１……内部電極（導電性セラミツク）、１２…
…内部電極（Pd，Ag−Pd合金等貴金属）。
1 to 4 are perspective views and cross-sectional views shown in the order of steps to explain the structure and manufacturing method of one embodiment of the present invention, and FIG. 1 is an exploded perspective view showing the laminated structure during thermocompression bonding. Figures 2 and 2 are cross-sectional views taken along line a-a' of the laminate shown in Figure 1 after thermocompression bonding, Figures 3 a to c are perspective views of individual green chips separated along the broken line in Figure 2, and their b -b' line and c-c' line, Fig. 4 is a perspective view of a multilayer ceramic capacitor with terminal electrodes formed, and Figs. 5 to 8 show the structure of a conventional multilayer ceramic capacitor and its manufacturing method. FIG. 9 is a perspective view and a cross-sectional view shown in the order of steps to explain the process, and FIG. 9 is a diagram showing the relationship between the series equivalent resistance of conductive ceramic and temperature. DESCRIPTION OF SYMBOLS 1... Raw sheet, 2... Protective layer, 3, 8... Laminated body, 4, 9... Raw chip piece, 5... Terminal electrode, 10, 20... Multilayer ceramic capacitor,
11... Internal electrode (conductive ceramic), 12...
...Internal electrode (noble metal such as P d , A g -P d alloy).
Claims (1)
上積み重ねた第１の生シート群と、前記第１の生
シート群の上下に保護絶縁層のみからなる第２の
生シート群を積層した積層セラミツクコンデンサ
素子において、前記内部電極にセラミツク導電体
｛Ba1-xYx｝CuO3（０≦ｘ≦１）を用いたことを
特徴とする積層セラミツクコンデンサ。1. A laminated ceramic, in which a first raw sheet group consisting of one or more raw sheets stacked with internal electrode patterns and a second raw sheet group consisting of only a protective insulating layer are laminated above and below the first raw sheet group. 1. A multilayer ceramic capacitor, characterized in that, in the capacitor element, a ceramic conductor {Ba 1-x Y x }CuO 3 (0≦x≦1) is used for the internal electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23161387A JPS6473608A (en) | 1987-09-14 | 1987-09-14 | Laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23161387A JPS6473608A (en) | 1987-09-14 | 1987-09-14 | Laminated ceramic capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6473608A JPS6473608A (en) | 1989-03-17 |
| JPH0515295B2 true JPH0515295B2 (en) | 1993-03-01 |
Family
ID=16926255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23161387A Granted JPS6473608A (en) | 1987-09-14 | 1987-09-14 | Laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6473608A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002091408A1 (en) * | 2001-05-08 | 2002-11-14 | Epcos Ag | Ceramic multi-layer element and a method for the production thereof |
| US7068490B2 (en) * | 2004-04-16 | 2006-06-27 | Kemet Electronics Corporation | Thermal dissipating capacitor and electrical component comprising same |
-
1987
- 1987-09-14 JP JP23161387A patent/JPS6473608A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6473608A (en) | 1989-03-17 |
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