JPS58211385A - Memory system - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to reduce the number of circuits as well as the mounting space, by using a single function circuit consisting mainly of a PROM to realize a circuit which selects the module of a memory system as well as an RAM array block. CONSTITUTION:A start address signal corresponding to the occupied address region of a memory module is set by a switch 105 and at the same time supplied to a coincidence circuit 114. These input signals are supplied to decoders 141 and 142 to be decoded. Then the addresses within PROM143-146 are designated. The output signal of the circuit 114 is supplied to a gate circuit 115, and a module selection signal is delivered by the output signal of the circuit 114 and the signal of a storage capacity designating switch 105 of the memory module. Thus the circuit consitution is simplified since both a module selecting circuit and an RAM block designating circuit can be constituted with the same circuit.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention 8A is a memory system, and the concrete t'c is the actual implementation efficiency in the memory 7 nodal selection and RAM block specification 71 functional circuits? Regarding improved memory/stem.

[Technical background of the invention and its problems]

Install two or more memory monolayers with an occupied address area and configure! memory 7 stem t
Selection of memory specialist soles constituting the memory/stem 41
< has conventionally been realized by a first-to-first circuit configuration.

By the way, the storage capacity of the 1-memory module is t, and it can be packed with different tc ones.Then, the seven-norm select circuit part becomes complicated as shown in Figure 2, and the circuit bowl and implementation are complicated. The drawback is that it requires a lot of space. After selecting the memory monoyl, the circuit system that determines which Glock in the RAM (random access memory) array is specified and driven is also increased. This had a negative impact on implementation efficiency.

Specifically, using FIGS. 1 to 3, we will briefly explain how to select a memory module in a conventional VC.

Figure 1 is a diagram of a typical memory/stem payout example 7J Squirrel Glock.

In the figure, I is the CPU, 2 is the pass line through which the address/1#-data/1tilJ Thl signal is transferred, and 3
4 is a module selection circuit, 4 is a bCt switch for each M, 5 is a switch for establishing a start location in the occupied address area of the seven memory nodes, 6 is a RAM block designation circuit, and 7 is a moshuno selection circuit. 3 output (Riru select) (Control circuit 4 that starts operation by Th number J3 and memory module start signal (Figure 7J-zera-9)) Output of circuit 6 (RA generated from No. 1 (line 9) and control circuit)
Buffer 12 driving 11 M blocks. ~1211 indicates a memory module.

FIG. 2 shows the internal structure of the 7 joule select circuit shown in FIG.

Fig. 3 compares the start address λ inch 5 and the address input gutter obtained from bus 2 with the address input gutter obtained from Dice and full size 'AL comparison circuit.

J 2 indicates the start address switch 5 is turned off. tIi1 Data obtained from each lid finger switch 4 , and the address input data sent from the samurai via the bus 2. 34 is a comparison circuit that determines whether the address data is smaller than 6. Figure 3 shows the RAM 7' Cl designation circuit shown in Figure 1, and the internal circuit of Figure 7. Mero.

Figure e (6) is a subtractor that calculates the difference between the address input data obtained via the bus 2 and the data of the start address switch 5, and 62 is the output of the subtractor 6. This is a decoder that encodes 1°.

Ten thousand times (Cl4.7 joules); r
.

The operation of the RAM 7'a and phase-specific circuit 6 will now be described.

In the monoyl select circuit, "), the memory monoyl prints the select awn t [whether or not it is selected or not, ?". RAM block finger syndrome circuit t; y < 2, - (this is what was being done).

Of the monoyl select circuit 3
, the start of the memory monologue, the setting redundancy, 1 notch 5 gives the r-tat illusion (2, bus 2 > power (
- The address that can be obtained is the address of the person Kara' - Evening or bamboo (if it is or is large, V (1 is activated, and the start 'grace' is set to 5 for the film. h
The Gundo circuit 34 is established if the address of the bus 2IJ-shi is 7. and module select (m % t 3 'l'' output.

The internal II movement block '1 of the RAM clock designation circuit 6 is connected to the bus 2.
When the address is entered via the address number 61, the address value of the start address switch 5 is reduced from the number 61 of the start address switch 5. Here, the subtracted kf-t is sent to the decoder 62 manually (
, T1ζAM clock signal V (number of forward block signals (line 9)) is fully output.

As mentioned above, conventionally, in order to select the desired memory, two comparator circuits, one adder or one (1ia)
, kM device or 1 piece, / Korg or 1 piece [θj1 AND circuit'
k 1 jIj·1 is required, the number of C-system elements is large compared to 4tl·, and the V mounting space is quite large.

[Purpose of the invention]

The present invention addresses the above-mentioned drawbacks, and the memory stem's seven seals or the RAM array block's 41 < 4 rows') )
I demonstrated this in a one-function circuit with ROM as the main component. 1n“
It's tb-like.

[Invention advisor]

This configuration is a RAM playback consisting of at least two memory nodes (obtained from the outside of the 7-stem memory VC, which is obtained from the outside of C1). A comparison between the signal and the target set by the start switch address is now possible.
It consists of OM, and the block selection is 1 from this FROM (c).
-), and it is set from this FROM output and the valley fil constant switch.

From this TL and K, the number of elements used is reduced 〃 Konogo [, 3 ゜ [departure ψ ”, which is easier to maintain and make it easier to maintain the monthly implementation efficiency] The present invention will be described in detail.

FIG. 4 is a block diagram showing the internal configuration of the functional circuit in which the invention is embodied, and specifically shows the select section of the memory module and the select section of the cock. C mei.

In the figure, reference numeral 102 is an address line S pass line sent from the CPU, and reference numeral 104 is a storage h1 of the memory monoyl.
Is the designated swing-1105 the start address for the Nannan address area of the memory module?3 fL
This is the first step.

714 il address (g%) Compare the address transferred via pass line 102 and the start address 4 notches 105 i/(yo!ll) to find a match. 109 is this The input signal is transmitted from the matching circuit 114 to the signal line 109, which is connected to the RAM array block 1.
No place H [The signal to be specified is transfer awn 7'L. 115
is the output of the matching circuit 114, and the select signal is output completely to the 16th row 13 by the Suinoteno 04 which adds all the memories of the memory monoyl) 6y-to circuit, 107
The above seven selections jt = %i (line 1
13) and starting the memory module "j (1g+7
This is a timing generation circuit that is activated by -C7'.

Also, 108 is the module select, block select circuit (--matching circuit) 14) uf warmer bow (line 109
), and the timing signal generated by the control circuit 107 iC drives the RAM Z1. Indicates the buffer to be ILIJ.

FIG. 5 illustrates the internal structure of the mano-14 at the same time as 7J< in FIG. 4. In the figure, 141 represents the "f address input" obtained via bus 102.

Decoder to decode, 1426 yosin f 5 QC
↓This is an r coder that codes the signal session that is set.

The output of the coder 142 is output from each FROM 143 to JJ6.
Supply hot water to T. 143 is the configuration of 0-pit ThfJ of PROM (7' programmatic pull-read memory), 144 is the configuration of 1-pit portion of FROM, and 145 is)
) Configuration of the 2-bit part of the ROM, 146Q to PROλ1
The 3rd pitch part of the 71st part is inside.

147-150 are pROM (J4:t-146)
The name indicates a bit of buffer gold.

Hereinafter, using Figures 4 and 5, we will explain the operation of 1) 1.psi. The address signal is input to the matching circuit 11Δ-, and on the other hand, the start address corresponding to the occupied address area of the memory monoyl is set by the switch 105, and the signal is input to the matching circuit 114. These input signals are supplied to decoders 141. and 142, where they are decoded and addresses in FROM 143-146 are designated.

It is assumed that 1 is stored in FROM (14, 9 to 146) in advance so that a °'l'' output is generated according to the following conditions.

Collection r for each address in FROM 143-146
As shown in FIG. 5, only when the address input from the bus 102 matches the designated signal data of the switches 105 It is inserted as instructed.

In addition, for the designation of block l, if the address input signal number is +1 for the designated No. 4N data, FRO
Make sure that M 144 outputs "1". In the case of block 2 specification below, when the address manual gutter becomes +20 value for the specified signal data, "1" output is used from FROM 145. In addition, in the case of specifying block 3, when the address input value becomes +3 for the specified signal data, the PROM 146 is written.
It is written in such a way that l'' output is generated.

The contents written in FROM 143 to 146 under the above conditions are shown in FIG. In the figure, the places (addresses) marked with ○ indicate the state in which data "1" has been written.

In the embodiment of the present invention, the case is illustrated in which address input data and designation signal data are each 2 bits, and block select signals are 4 signals.

Generally, the address input signal of the monoyl select circuit section is used to focus on the upper address bits that specify the internal phase of the RAM/ICC. Therefore, it uses 16KRAMk and the word length is 1.
In the case of 6 bits, the configuration of one block is 32 bits, by I, and so on, so the upper bits of the address excluding the 17 bits become the address input to the matching circuit 114.

The output signal of the matching circuit 114 is inputted to the gate circuit 11.5V, and the signal of the memory mono/σ storage capacity designation switch 104 and Q' are thereby generated as the module select signal (
line 113) is output. The monole select signal is a signal that means that the memory monole has been set, and the timing generation circuit 107 outputs the 11 signal.
The operation is started by a number and a memory start toy number 8 (not shown).

When the timing generation circuit 107 generates various timing signals, the timing signal and the block designation signal outputted from the coincidence circuit 114 (line J o 9) are generated.
The buffer 108 operates according to the I/'C, and the corresponding R
The AM block is driven.

As can be seen from the above description, compared to the conventional module select signal and RAM block designation circuit, the embodiment of the present invention requires fewer circuit elements and improves the mounting efficiency of the memory monole.

The coincidence circuit 114 can be realized with one IK×4-bit FROM.

It should be noted that the present invention has a complete monochrome matching circuit built-in for each monole, and is effective for equipment in which a plurality of blocks having the same configuration are included inside the monole.

〔Effect of the invention〕

As described above, according to the present invention, the monoyl select circuit and the RAM block designation circuit of the memory module are configured by the same circuit (FROM IC), and therefore the number of circuit elements is significantly reduced. This improves implementation efficiency and also facilitates maintenance.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an example of the configuration of a normal memory stem, and Figure 2 is the internal configuration of the module select circuit in Figure 1. The block diagram shown in Figure 3 is R in Figure 1.
Internal configuration of AM block designation circuit? 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing the entire internal configuration of the matching (b) path in the figure. 104.105-・Su4nona, 11 '4・・Concordance circuit, trs・r-) circuit, 143~ノ46・PROM0 Applicant's agent Bene (41st person Takehiko Suzu 15th
1 1125! ! 1 Figure 3 Figure 114

Claims (1)

[Claims] In a memory system consisting of a plurality of memory blocks each consisting of a RAM array of at least two blocks, the first address generally located in the 6 south address area of the memory block is switch and upper 5L
The capacity of the 2-memory monoyl is set by the second switch, the address signal coming from the outside, and the 1st notch of the upper self. mlRAM 7 rays based on the contents of 1t
Address to choose from? Output No. I: I Grammar Pull 1 (OM, *, Gramagle ROM output and the case that selects the above memory monologue based on the value set in the second switch) It is equipped with 7 memory stems that can be used as images.