JPH043394A - Semiconductor non-volatile storage device - Google Patents

Abstract

PURPOSE:To collectively erase one or more selected blocks to shorten the erase time by providing a word line decoding circuit with latch circuits which can be selectively set by a block address. CONSTITUTION:A word line decoding circuit 101 is provided with latch circuits 102, 103, and 104. The block address is selected by an address decoder 114. When blocks 111 and 112 will be erased, latch circuits 102 and 103 are set by the block address, and blocks 111 and 112 are simultaneously erased with one erase operation. The block 113 is not erased in this case because the latch circuit 104 is not set, and plural blocks are selectively erased. Though two blocks are collectively erased, one or more arbitrary blocks can be selectively and collectively erased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically rewritable semiconductor non-volatile memory device, and more particularly to improving the erase time of a semiconductor non-volatile memory device.

[Conventional technology]

Electrically rewritable semiconductor nonvolatile memory devices have a problem in that it takes a long time to erase stored data due to the electrical characteristics of the built-in nonvolatile memory elements. Conventionally, in order to solve this problem, the erase time is reduced equimetrically by erasing multiple nonvolatile memory elements at once in a single erase operation, such as the page erase method, block erase method, and chip-batch erase method. A shortening method is being adopted.

The page erase method is a method that erases all nonvolatile memory elements connected to one word line selected by a page address at once, and the block erase method is a method that erases all of the nonvolatile memory elements connected to one word line selected by a is a method of erasing all nonvolatile memory elements in a group of two or more word lines at once. The chip-batch erase method is a method for erasing all nonvolatile memory elements in a nonvolatile semiconductor memory device at once.

[Problem to be solved by the invention]

In the block erase method, only one block can be erased in one erasing operation, so when erasing multiple blocks, multiple erasing operations are required, which increases the erasing time. Furthermore, since the page erase method can erase only one page in one erase operation, erasing multiple pages requires multiple erase operations, which increases the erase time. In the chip-batch erase method, blocks or pages that do not need to be erased are also erased, so the blocks or pages that do not need to be erased must be rewritten.

An object of the present invention is to eliminate such drawbacks and provide a semiconductor nonvolatile memory device with short erasing time.

[Means to solve the problem]

In order to achieve the above object, the present invention provides the following device. (a) A latch circuit that can be selectively set by block address is provided in the word line decoder circuit,
A semiconductor nonvolatile memory device characterized in that one or more selected blocks are erased at once. (b) A semiconductor nonvolatile memory device characterized in that a latch circuit that can be selectively set by a page address is provided in a word line decoder circuit, and one or more selected pages can be erased at once.

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 1 is an example of the circuit configuration of a semiconductor nonvolatile memory device in which a launch circuit that can be selectively set by a block address is provided in a word line decoder circuit according to the present invention. The memory cell circuit is MNOS (Metal-Nitride)
-Oxide-8emiconductor) type or MONO8 (Metal-Oxide-Nitride) type
This is an example in which a nonvolatile memory element 116 of a type (-Oxide-8emiConduCtor) and an address element 117 are connected in series. Although one block in FIG. 1 has a two-page structure, it is clear from the following description that it can be extended to a semiconductor nonvolatile memory device in which one block has three or more pages. In FIG. 1, a word line decoder circuit 101 includes an address decoder circuit 114, a word line driver circuit 115, a word line 105, and a word line 10.
6 and the launch circuit 102 connected to the word line 107A.
A latch circuit 106 is connected to a '7- word line 108, and a latch circuit 104 is connected to a word line 109 and a word line 110. The block address is selected by address decoder circuit 114. When erasing blocks 111 and 112, latch circuits 102 and 103 are set with block addresses, and blocks 111 and 112 are simultaneously erased in one erasing operation. At this time, the latch circuit 104
Blocks 116 for which the is not set are not erased, and multiple blocks can be selectively erased.

In the above embodiment, two blocks are erased at once, but by using the present invention, it is possible to selectively erase one or more blocks at once.

FIG. 2 is an example of the circuit configuration of a semiconductor nonvolatile memory device in which a latch circuit that can be selectively sent by a page address is provided in a word line decoder circuit according to the present invention. The memory cell circuit is an example in which an MNOS type or MONO8 type nonvolatile memory element 213 and an address element 214 are connected in series. The word line decoder circuit 201 includes an address decoder circuit 211, a word line driver circuit 212, and a latch circuit 20 connected to the word line 205.
2. A latch circuit 206 connected to a word line 206 and a launch circuit 204 connected to a word line 207 are provided. The page address is selected by the address decoder circuit 211.

When erasing page 208 and page 209, the latch circuit 202 and latch circuit 206 are set with the page address, and page 208 and page 209 are erased in one erase operation.
9 and 9 at the same time. At this time, pages 210 for which the latch circuit 204 is not set are not erased, and a plurality of pages can be selectively erased. In the above embodiment, two pages are erased at once, but by using the present invention, it is possible to selectively erase one or more arbitrary pages at once.

FIG. 3 is an example of a circuit configuration of a latch circuit according to the present invention. FIG. 3 consists of inverter circuits 601 and 602, a set input quadrant register 06, and a reset input quadrant register 04, and the block address or page address is used.

〔Effect of the invention〕

As described above, the present invention makes it possible to reduce the time required to erase multiple blocks or multiple pages of data in a semiconductor nonvolatile memory device compared to the conventional technology. In other words, the speed of the semiconductor nonvolatile memory device can be increased.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor non-volatile memory device according to the present invention that can erase multiple blocks at once, and FIG. 2 is a circuit diagram of a semiconductor non-volatile memory device that can erase multiple pages at once according to the present invention. FIG. 3 is a circuit diagram of the latch circuit. 101.201...Word line decoder circuit, 1
02.103.104.202.203°204...
...Launch circuit, 111.112.113...Block, 208
．． 209.210...page. 201 Word gland coater circuit 202, 203.2Q4 2-f circuit 208, 209.21 ON-di

Claims (2)

[Claims] (1) A semiconductor nonvolatile memory device characterized in that a word line decoder circuit is provided with a latch circuit that can be selectively set by a block address, and one or more selected blocks are erased at once. (2) A semiconductor nonvolatile memory device characterized in that a latch circuit that can be selectively set by a page address is provided in a word line decoder circuit, and one or more selected pages are erased at once.