JPH01298600A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To efficiently and rapidly rewrite a part of areas in an inner storage element by providing the title device with a storage circuit for selecting the optional number of blocks to be erased and a block erasing circuit for applying a block erasing signal to the selected blocks. CONSTITUTION:The storage area of the inner storage element 11 is divided into n blocks 111-11n and a batch erasing circuit 12 is connected to these blocks. In addition, a decoder circuit 13 is connected to the blocks 111-11n to decode an address signal applied from the external, select optional one or plural blocks out of the blocks 111-11n and collectively erase the contents of all the selected blocks. A storage circuit 16 changes its state by a block selection signal outputted from a block selection circuit 15, determines the block to which a signal is applied and impress a block erasing signal only to the determined block. Thereby succeeding writing is executed only in the erased blocks, so that the erasing and writing time can be shortened.

Description

[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a semiconductor memory device.

(Prior Art) FIG. 5 shows an example of a nonvolatile semiconductor memory device having an internal memory element that can be electrically written and erased n1. A read circuit 2, a write circuit 3, and an erase circuit 4 are connected to the internal storage element (cell) 1.

Reading, writing, and erasing are performed by each of these circuits 2 to 4. The erasing methods used by the erasing circuit 4 include (1) the first h method in which each storage area of an element is erased;

■ The second method is to erase all memory areas of the device at once.

There were two methods.

(Issue 8 to be Solved by the Invention) The two conventional electrical erasing methods, the first and second, each have the following problems.

That is, a. The first method has the problem that erasing time becomes longer if the number of memory areas of the element is large. Moreover, as the number of these areas increases, there is a problem in that the erasing time also increases.

b. In the second method, if the method is adopted for rewriting data on a part of the element, the data can be erased all at once, but then the data on all the areas can be rewritten. There is a problem in that writing has to be performed again, and it takes a lot of time to write to all the areas.

The present invention has been made in view of the above, and its purpose is to:
An object of the present invention is to provide a semiconductor memory device that can efficiently rewrite a part of an area of an internal memory element in a short time.

(Means for Solving the Problems) A semiconductor memory device of the present invention includes electrically writable and erasable non-volatile internal memory elements, in which the internal memory elements can be written to and erased independently of each other. and is divided into a plurality of erasable blocks,
Further, a block selection circuit that outputs a block selection signal for selecting an arbitrary number of blocks to be erased from among the blocks, and a storage circuit that stores the block selection signal and selects the arbitrary number of blocks to be erased. and a block erase circuit that applies a block erase signal to the selected block.

Further, the storage circuit is configured to change its state based on a block selection signal from the block selection circuit and decide to which block the block erasure ta from the block erasure circuit is applied.

(Operation) The internal storage element is divided into a plurality of blocks that can be written and erased independently of each other. A block selection signal for selecting an arbitrary number of blocks to be erased is output from the block selection circuit. The block selection signal is stored in the storage circuit, and an arbitrary number of blocks are selected.

A block erase signal is applied to the selected block by the block erase circuit. That is, the storage circuit changes its state in response to a block selection signal from the block selection circuit, determines which block is to be added, and applies block erase No. 1g only to the determined block. As a result, only the selected arbitrary number of blocks are erased. Therefore, future writing can be performed on the erased block. This reduces erasing and writing time.

(Embodiment) FIG. 1 is an overall configuration diagram of an embodiment of the present invention. In the figure, 11 is an internal storage element.

In the cable 11, the storage area of the element is divided into n blocks 111 to 11n. A batch erase circuit 12 is connected to these blocks 111 to 11n. The contents of all blocks 111-11 are erased at once by the erase signal from the batch erase circuit 12.

Furthermore, the blocks 111 to 11n include a decoder circuit 13.
is connected. The decoder circuit 13 decodes the address signal applied from the outside and blocks 11.
-11o is selected, and the contents of all the selected blocks are erased at once.

That is, what does the decoder circuit 3 do for the block selection circuit 15? The block selection circuit 15 decodes the address signal applied from the outside and applies it to the nonvolatile storage circuit 16 at the next stage. The memory circuit 16 includes the block selection circuit 15
The first output line 161 to 16□ is outputted to any one or more of the first output lines 161 to 16□ according to the signal. The first output is the next-stage AND gate 171~
It is applied to one input terminal of any one of 17. Their AND gate17. A block erase signal from the block erase circuit 18 is applied to the other input terminal of .about.17□. As a result, AND gates 17, ~1
A second output (erase voltage) is output to the second output line 19□ to 19° to which the first output of 7□ is applied. A second output is applied to blocks 11-11 through second output lines 19, .about.19n. Blocks 111-i
The contents of an arbitrary number of blocks of n 11 to which the second output is added are erased all at once.

FIG. 2 is a circuit diagram showing a specific example of the chain line portion in FIG. 1. As can be seen from FIG. 2, the memory circuit 16 is configured to include a plurality of nonvolatile elements 16a. Furthermore, in FIG. 2, the AND gate 17
An amplifier 21 is used as the block selection circuit 5, and the second output is obtained when the output from the block selection circuit 5 and the erase voltage VEP are ANDed. If the nonvolatile element 16a is not written and is in a conductive state, the erase voltage VEP (second output) is not output from the second output line 191. Furthermore, when the nonvolatile cable 16a is in a non-conductive state due to writing, the erase voltage vEP is set to the second level.
It is output as the second output from the output line 191 and is output from block 1.
11 is deleted.

Therefore, by writing to the nonvolatile element 16a corresponding to the block to be erased among the blocks 111 to 11n, the blocks to be erased can be erased all at once.

FIG. 3 shows E P as the nonvolatile element 16a in FIG.
The case where a device with ROM 16 a J is used is shown. To select only block 11□, select all E
Writing (injection of hot electrons into hot electrons) is performed only in E PROM 1.6 a 1 of the PROMs. As a result, when the normal power supply voltage V is applied, only the EPROM 16 a 1 has C in a non-conducting state, and the other EPROMs (not shown)
is in a conducting state. In this state, when the block erase circuit 18 outputs the erase voltage vEP, E P R
Since OM 16 a 1 is in a non-conductive state, its erase voltage vEP is directly applied to block 11 □,
Erasure is performed. On the other hand, since the other EPROMs are in a conductive state, the erase voltage vEP is dropped by the resistor R and is not applied to the other blocks 11□ to 11n, so that erasure is not performed. Therefore, the block you want to erase (111
By writing in advance to the EFROM corresponding to 11), it is possible to erase only the blocks that are desired to be erased at once. Writing and erasing of EPROM is performed by irradiation with ultraviolet rays.

However, if erasing cannot be done by irradiation with ultraviolet rays, such as when packaging is done so that ultraviolet rays cannot pass through, EEPROM may be used instead of EFROM.

FIG. 4 shows an example of such a case. E E
Erasing of the PROM 26a1 is electrically performed by a reset signal output from the reset signal output circuit 26b.

In this way, a specific arbitrary number of blocks in the internal storage element 11 are erased all at once. After this, it is only necessary to write to the block from which In has been removed.

According to the above embodiment, the following effects can be obtained.

(1) Improvement of problem a of the prior art (1) According to the prior art (2), erasing time increases in proportion to the number of storage areas of the device. However, according to the above embodiment, since the storage areas to be erased are erased all at once, the erasing time can be shortened accordingly.

(2) Improvement of the problem of the prior art (2) According to the prior art (2), even when rewriting a part of the memory area of an element, all the memory areas must be erased; It was necessary to write to this area. However, according to the above embodiment, it is only necessary to write to the erased storage area, which shortens the write time.

〔Effect of the invention〕

According to the present invention, the internal memory element is divided into a plurality of blocks, and only one or more of these blocks can be erased at once, so that only a part of the internal memory element can be erased. When performing rewriting, only the necessary portions are erased and rewritten, and the time required for rewriting can be minimized without wasting any waste.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention, FIG. 2 is a circuit diagram embodying a part thereof, and FIGS. 3 and 4 are circuit diagrams showing different specific examples thereof. FIG. 5 is a block diagram of a conventional example. 11... Internal storage element, 11□-11. ... block, 13 ... decoder, 15 ... block selection circuit, 16 ... memory circuit, 18 ... block erase circuit. Applicant's agent Mr. Sato Figure 5

Claims (1)

[Claims] 1. In a semiconductor memory device having a nonvolatile internal memory element that can be electrically written to and erased, the internal memory element is divided into a plurality of blocks that can be written to and erased independently of each other. further comprising: a block selection circuit that outputs a block selection signal for selecting an arbitrary number of blocks to be erased from among the blocks; and a block selection circuit that stores the block selection signal and selects the arbitrary number of blocks to be erased. A semiconductor memory device comprising: a memory circuit that selects a block; and a block erase circuit that applies a block erase signal to the selected block. 2. The memory circuit changes its state based on the block selection signal from the block selection circuit, and determines to which block the block erasure signal from the block erasure circuit is applied. semiconductor storage device.