JPS5697145A - Operation control device - Google Patents

Operation control device

Info

Publication number
JPS5697145A
JPS5697145A JP17349079A JP17349079A JPS5697145A JP S5697145 A JPS5697145 A JP S5697145A JP 17349079 A JP17349079 A JP 17349079A JP 17349079 A JP17349079 A JP 17349079A JP S5697145 A JPS5697145 A JP S5697145A
Authority
JP
Japan
Prior art keywords
rom4
address
5aw5n
subprogram
blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17349079A
Other languages
Japanese (ja)
Inventor
Katsutoshi Okayasu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Takeda Riken Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp, Takeda Riken Industries Co Ltd filed Critical Advantest Corp
Priority to JP17349079A priority Critical patent/JPS5697145A/en
Publication of JPS5697145A publication Critical patent/JPS5697145A/en
Pending legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: To make easy the change in the subprogram without giving effect on the main program, by providing ROM having a plurality of memory blocks, and selecting the readout output of ROM with the gate circuit.
CONSTITUTION: RAM2 and the 1st ROM3 and the subprogram storing the main program are stored in CPU1 via the address bus 8 and the data bus 7. The 2nd ROM4 is connected, which is constituted with the memory blocks 5aW5n. In reading out the program of the blocks 5aW5n of ROM4, an address is given from the address 8, the gate circuits 6a, 6n are selected with the address interpreted with the decoder 9, and the output of the blocks 5aW5n of ROM4 is output to the data bus 7. Further, without giving effect on the main program stored in ROM3, the change in the subprogram of ROM4 can easily be made.
COPYRIGHT: (C)1981,JPO&Japio
JP17349079A 1979-12-29 1979-12-29 Operation control device Pending JPS5697145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17349079A JPS5697145A (en) 1979-12-29 1979-12-29 Operation control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17349079A JPS5697145A (en) 1979-12-29 1979-12-29 Operation control device

Publications (1)

Publication Number Publication Date
JPS5697145A true JPS5697145A (en) 1981-08-05

Family

ID=15961466

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17349079A Pending JPS5697145A (en) 1979-12-29 1979-12-29 Operation control device

Country Status (1)

Country Link
JP (1) JPS5697145A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63187498A (en) * 1987-01-28 1988-08-03 Nec Corp Read only memory device capable of being programmed for plural number of times

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5096131A (en) * 1973-12-22 1975-07-31
JPS50155146A (en) * 1974-06-03 1975-12-15
JPS5148951A (en) * 1974-10-25 1976-04-27 Hitachi Ltd
JPS5617440A (en) * 1979-07-23 1981-02-19 Fujitsu Ltd Memory sharing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5096131A (en) * 1973-12-22 1975-07-31
JPS50155146A (en) * 1974-06-03 1975-12-15
JPS5148951A (en) * 1974-10-25 1976-04-27 Hitachi Ltd
JPS5617440A (en) * 1979-07-23 1981-02-19 Fujitsu Ltd Memory sharing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63187498A (en) * 1987-01-28 1988-08-03 Nec Corp Read only memory device capable of being programmed for plural number of times

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