JPS5539966A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5539966A
JPS5539966A JP11276678A JP11276678A JPS5539966A JP S5539966 A JPS5539966 A JP S5539966A JP 11276678 A JP11276678 A JP 11276678A JP 11276678 A JP11276678 A JP 11276678A JP S5539966 A JPS5539966 A JP S5539966A
Authority
JP
Japan
Prior art keywords
data
circuit
external processing
circuits
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11276678A
Other languages
Japanese (ja)
Inventor
Kenji Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11276678A priority Critical patent/JPS5539966A/en
Publication of JPS5539966A publication Critical patent/JPS5539966A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To carry out the memory of the data without changing the circuit when the transmission width of the data given from the external processing device is changed by duplicating the receiving terminal of the writing data in a basic system circuit of the data control circuit.
CONSTITUTION: The data from M×N block (M, N are integer) is divided into M groups every N blocks and in the case of transmission between the external processing devices, the data is memorized in a divided area into M×N of the memory device 44. To this device 44, the N blocks of basic system circuits 40W43 are connected and the decoder circuit 57 for controlling the wired logic circuit to the circuits 40W43. By the blcock position specification control circuit 21 disposed to the respective circuits 40W43 of this construction, the access from the external processing device to the respective data memory area of the device 44 is made, and by the wired logic circuit 36, the output from the external processing device is outputted and transmitted or the output level is floated and the data is divided into M groups every N block for processing.
COPYRIGHT: (C)1980,JPO&Japio
JP11276678A 1978-09-12 1978-09-12 Memory device Pending JPS5539966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11276678A JPS5539966A (en) 1978-09-12 1978-09-12 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11276678A JPS5539966A (en) 1978-09-12 1978-09-12 Memory device

Publications (1)

Publication Number Publication Date
JPS5539966A true JPS5539966A (en) 1980-03-21

Family

ID=14594971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11276678A Pending JPS5539966A (en) 1978-09-12 1978-09-12 Memory device

Country Status (1)

Country Link
JP (1) JPS5539966A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61132582A (en) * 1984-11-30 1986-06-20 有限会社　大倉製作所 Chicken excrements processing machine
JPH04114712U (en) * 1991-03-25 1992-10-09 矢崎総業株式会社 cable lifting jig

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61132582A (en) * 1984-11-30 1986-06-20 有限会社　大倉製作所 Chicken excrements processing machine
JPH0134958B2 (en) * 1984-11-30 1989-07-21 Ookura Seisakusho Jugen
JPH04114712U (en) * 1991-03-25 1992-10-09 矢崎総業株式会社 cable lifting jig

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