JPS54110743A - Electronic apparatus - Google Patents

Electronic apparatus

Info

Publication number
JPS54110743A
JPS54110743A JP1733578A JP1733578A JPS54110743A JP S54110743 A JPS54110743 A JP S54110743A JP 1733578 A JP1733578 A JP 1733578A JP 1733578 A JP1733578 A JP 1733578A JP S54110743 A JPS54110743 A JP S54110743A
Authority
JP
Japan
Prior art keywords
data
delivered
address
control
bus line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1733578A
Other languages
Japanese (ja)
Inventor
Kunio Yasutake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP1733578A priority Critical patent/JPS54110743A/en
Publication of JPS54110743A publication Critical patent/JPS54110743A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To reduce the number of the terminal through sharing of the address data and control data output terminals by using the same address bus for the transfer of both the address data and the control data.
CONSTITUTION: Both the address data and the control data are delivered to the common bus line from control part 35 via the common terminal. At the same time, the signal showing the data delivered to the common bus line is the address data or the control data is delivered via switching of selector 36. In case the data delivered to the common bus line is shown as the control data by the above mentioned signal, the data is decoded and plural flip-flops are controlled to deliver the prescribed control command. While if the data delivered to the common bus line is the address data, the data is transferred to the memory circut in the form of the address data.
COPYRIGHT: (C)1979,JPO&Japio
JP1733578A 1978-02-17 1978-02-17 Electronic apparatus Pending JPS54110743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1733578A JPS54110743A (en) 1978-02-17 1978-02-17 Electronic apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1733578A JPS54110743A (en) 1978-02-17 1978-02-17 Electronic apparatus

Publications (1)

Publication Number Publication Date
JPS54110743A true JPS54110743A (en) 1979-08-30

Family

ID=11941171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1733578A Pending JPS54110743A (en) 1978-02-17 1978-02-17 Electronic apparatus

Country Status (1)

Country Link
JP (1) JPS54110743A (en)

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