JPS58206121A - Manufacture of thin-film semiconductor device - Google Patents
Manufacture of thin-film semiconductor deviceInfo
- Publication number
- JPS58206121A JPS58206121A JP9006782A JP9006782A JPS58206121A JP S58206121 A JPS58206121 A JP S58206121A JP 9006782 A JP9006782 A JP 9006782A JP 9006782 A JP9006782 A JP 9006782A JP S58206121 A JPS58206121 A JP S58206121A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- island
- film
- substrate
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000010408 film Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000004913 activation Effects 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- AFYNYVFJTDCVBJ-UHFFFAOYSA-N [Si].[S] Chemical compound [Si].[S] AFYNYVFJTDCVBJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野」
本発明は、基板上に堆積したシリコンミｌ膜を能動領域
として用いる４膜半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a four-film semiconductor device using a silicon mil film deposited on a substrate as an active region.
非晶質基板上の薄膜シリコン半導体装置の実用化への最
大の難点は、電気的特性が単結晶シリコン半導体装置に
比べて者しく劣っていることである。その理由は、シリ
コン薄膜の結晶性にある。非晶質基板、特にプラスを基
板としたシリコン薄膜は、非ｌ＃＆質、微結晶あるいは
粒径敬白゛Ｘの多結晶状態である。このようなシリコン
薄膜の電気的特性は単結晶シリコンのそれに比べて著し
く悪く、キャリア移動度は１ ｃｒｒ？ｌデｌｅｅ以下
であり単結晶シリコンに比べて数百分の１の値にすぎな
い。The biggest difficulty in putting thin-film silicon semiconductor devices on an amorphous substrate into practical use is that their electrical characteristics are significantly inferior to those of single-crystal silicon semiconductor devices. The reason for this is the crystallinity of the silicon thin film. A silicon thin film using an amorphous substrate, especially a positive substrate, is in a non-I# crystalline, microcrystalline, or polycrystalline state with a grain size of X. The electrical properties of such a silicon thin film are significantly worse than those of single crystal silicon, and the carrier mobility is 1 crr? It is less than 1 de lee, which is only several hundred times lower than that of single crystal silicon.
シリコン薄膜の電気的特性を向上させる方法は、結晶粒
径の大きい多結晶状態にすることであり、理想的には更
に結晶粒径の大きい単結晶にすることである。そのため
には、シリコン薄膜の堆積ｆｌｉ！Ｉ＃：金高くするこ
と、あるいは、堆積中のシリコンに何らかの方法でエネ
ルギーを供給することが考えられる。A method of improving the electrical properties of a silicon thin film is to make it into a polycrystalline state with a large crystal grain size, and ideally, to make it into a single crystal state with an even larger crystal grain size. For this purpose, a thin silicon film must be deposited! I#: It is possible to make the gold more expensive or to somehow supply energy to the silicon being deposited.
しかし、非晶質基板とじてガラスを用いた場合、堆積温
度には上限があり、例えばコーニングア０５９では約５
５０℃が最高堆積温度である。この温度を越えてシリコ
ンの堆積を行なうとガラス板が変形してし埜いそれ以降
の製造工程でのフォトリングラフィが不ロ■Ｈ目になる
。However, when glass is used as the amorphous substrate, there is an upper limit to the deposition temperature; for example, for Corning A059, the deposition temperature is approximately 5
50°C is the maximum deposition temperature. If silicon is deposited above this temperature, the glass plate will be deformed and the photolithography in the subsequent manufacturing process will be poor.
薄膜シリコン十傳体に要求されるキャリア移動度は少な
くとも１０ｒｉ／マ・１０以上であり、その条件を満す
Ｑ′こは、ンリコン堆積温度は通常のＣＶＤ法、あるい
はス′＝′と装有法を用いても７００℃以下にすること
はｊ＋１６かしい。便って低温でプラス吸上に堆積され
た／リコン薄ｌＩ＃を何らかの方法で結晶粒径の大きい
シリコン博映に変えなければならない。The carrier mobility required for a thin-film silicon matrix is at least 10 ri/ma. Even if you use the method, it is difficult to lower the temperature to below 700°C. Therefore, the thin lI# deposited on a positive wick at low temperatures must be converted into silicon with a large grain size by some method.
本発明は、上記の点に轟み、４漠シリコン半導体装置の
′Ｉｔ気的詩的特性しく同上させることの出来る製造方
法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention addresses the above-mentioned points and aims to provide a manufacturing method capable of achieving all the characteristic characteristics of a silicon semiconductor device.
〔発明の概要〕 １・
本発明は、基板上に欄、嘴形成した島状シリコン唄硫に
イオン注入マスクを経た僕、エネルギービームを照射す
ることにより、シリコンの、ＭＡ粒径の増大を促進させ
ると同時に、シリコン中ＶＣ注入された不純物原子の電
気的な活性化を促進することを特徴とする。[Summary of the Invention] 1. The present invention promotes the increase in the MA grain size of silicon by irradiating an energy beam through an ion implantation mask to island-shaped silicon sulfur formed on a substrate. At the same time, it promotes electrical activation of impurity atoms implanted into silicon.
本発明により、非晶質基板上に形成された薄膜シリコン
半導体素子の電気的特性の大幅な改善が可能になった。The present invention has made it possible to significantly improve the electrical characteristics of thin film silicon semiconductor devices formed on amorphous substrates.
例えばチャンネル長（Ｌ）が２０ｔｕｎ、チャンネルＩ
ＩＩ！（Ｗ）が２０ ａｍ、ｒ−ト酸化膜厚１５００Ｘ
のｎチャンネルエンハンスメント型ＭＯ８ＦＥＴの特性
は、レーザー光照射によシしきい値電圧（７丁）が１８
Ｖから２，５Ｖに減少し、実効移動度（μｅｆｆ）が、
０．１ ｃｔｎ２／Ｙ’ｌ＠ｅから１６ ＣＩＩＬ”／
ｖ・ｓ＊ｅと１６０倍の増加を示した。またシリコン膜
の平均結晶粒径も３００〜５００Ｘであったものが、レ
ーデ光照射後は０、５〜１．０μｍと増大していた。ソ
ースドレーン領域は燐イオンを２×１０１５／ｃＩＩＬ
２注入した場合、レーデ光照射後のシート抵抗値は１５
０〜２５０ Ｑ１０、活性化率８０〜９０％の低抵抗ｎ
＋多結晶シリコンになっていた。For example, channel length (L) is 20tun, channel I
II! (W) is 20 am, r-to oxide film thickness 1500X
The characteristics of the n-channel enhancement type MO8FET are that the threshold voltage (7 pins) is 18 when irradiated with laser light.
V to 2.5 V, the effective mobility (μeff) is
0.1 ctn2/Y'l@e to 16 CIIL"/
It showed a 160-fold increase in v·s*e. Furthermore, the average crystal grain size of the silicon film was 300 to 500X, but after irradiation with Raded light, it increased to 0.5 to 1.0 μm. The source/drain region contains phosphorus ions at 2×1015/cIIL.
2, the sheet resistance value after irradiation with Rede light is 15
0-250 Q10, low resistance n with activation rate 80-90%
+ It was made of polycrystalline silicon.
以下に図面を参照して本発明の実施例を述べる。本実施
例では、非晶簀基板としてコーニンＳｉＨ４の熱分解に
よる常圧←＃→法で堆積した。Embodiments of the present invention will be described below with reference to the drawings. In this example, the amorphous substrate was deposited by the normal pressure←#→ method using thermal decomposition of Konin SiH4.
その時の基板温度は５３０℃であり、膜厚０，６〜０．
７ ｔｍ、平均結晶粒径３００〜５００Ｘ、キャリア移
動度は０．１５ ｃ３ｎ２／ｖ・ｌｅｅであった。The substrate temperature at that time was 530°C, and the film thickness was 0.6~0.
7 tm, an average crystal grain size of 300 to 500X, and a carrier mobility of 0.15 c3n2/v·lee.
第１図は、ガラス基板１上に堆積したシリコン薄膜２を
ＦＥＴとして必要な形状にエツチングした後、二酸化ケ
イ＄（ＳｉＯ２）膜３を絶縁膜と３は、常圧セ弁呼法で
堆積し、その時の基板温度４３０℃、膜厚は１５００Ｘ
であった。ま九この二酸化ケイ素膜３は、ＦＥＴのｙ−
ト絶縁膜として、ｍａｔで残しておくものである。FIG. 1 shows that after a silicon thin film 2 deposited on a glass substrate 1 is etched into the shape required for an FET, a silicon dioxide (SiO2) film 3 is deposited as an insulating film by the atmospheric pressure separation method. , the substrate temperature at that time was 430℃, and the film thickness was 1500X.
Met. This silicon dioxide film 3 is the y-
The mat is left as an insulating film.
第２図は、二酸化ケイ素３膜を通して、ソース、ドレー
ン領域６，７に選択的にイオン注入５を付なっている状
！Ｉ１４を示す。ＦｇＴのチャンネル領域へのイオン注
入マスクには、淳さ１μｍ程褪０レノストマスク４を１
史用している。ソース、ドレーン領域の抵抗は、充分低
くする必要があり、この場合は、燐（Ｐ）を１５０ ｋ
ｓＶの加速エネルギーで、シリコン中の注入菫がおよそ
２ Ｘ １０ ／ｃｒｎ”になるようイオン注入した
。In Figure 2, ion implantation 5 is selectively applied to the source and drain regions 6 and 7 through the silicon dioxide 3 film! I14 is shown. For the ion implantation mask into the FgT channel region, a Rennost mask 4 with a thickness of about 1 μm was used.
Historically used. The resistance of the source and drain regions must be sufficiently low. In this case, phosphorus (P) is
Ions were implanted at an acceleration energy of sV so that the implantation density in silicon was approximately 2 x 10 /crn''.
第３図は、先のレジストマスク４を剥離した後に、イオ
ン注入工程が終了した島状シリコン領域にレーザー光８
を照射している状態を示している。レーザー照射条件は
、出力６ＷのＣＷＡｒレーデ−から放出される波長５１
４５Ｘの光線をおよそ２００μｍφ（レーザー管端では
、およそ２■φ）に集光し、走査速度６０ ｃｍＡｎ
ｉ ｎ、走査光の重なりは１０μ％／５ｔｏｐとした。FIG. 3 shows that after the resist mask 4 has been peeled off, a laser beam 8 is applied to the island-like silicon region where the ion implantation process has been completed.
This shows the state in which the light is being irradiated. The laser irradiation conditions are a wavelength of 51 emitted from a CWAr radar with an output of 6W.
A 45X light beam was focused on approximately 200 μmφ (approximately 2 mmφ at the end of the laser tube), and the scanning speed was 60 cmAn.
In, the overlap of the scanning lights was set to 10 μ%/5top.
この結果、シリコン薄膜中では、結晶成長が促進され、
膜の平均結晶粒径は３００〜５００Ｘの微結晶から、０
．５〜１μｍの大きさに増大し、シリコン膜は着しい（
２２０）配向を持った多結晶シリコン薄膜に変化する。As a result, crystal growth is promoted in the silicon thin film,
The average crystal grain size of the film ranges from 300 to 500X microcrystals to 0.
．． The size increases to 5 to 1 μm, and the silicon film becomes thick (
220) Transforms into an oriented polycrystalline silicon thin film.
また、燐（Ｐ）イオンが注入されたソース、ドレーン領
域６，７では、結晶成長と同時に燐原子のシリコン格子
位置への１ａ侯が進行し、１気的な活性化率８０〜９０
チ、シート抵抗１５０〜２５０ ｒＶＯの低抵抗口形多
結晶シリコンが形成されていた。In addition, in the source and drain regions 6 and 7 into which phosphorus (P) ions are implanted, phosphorus atoms move to silicon lattice positions at the same time as crystal growth, and the activation rate is 80 to 90.
A low-resistance polycrystalline silicon having a sheet resistance of 150 to 250 rVO was formed.
第４図は、レーザー光照射終った後、先に堆積しておい
て、二酸化ケイ素膜３上に、ソース、ドレーンおよびｙ
−トの各電極９，１０および１１’ｚ形成した様子を示
す、各電甑９〜１ノは、ソース、ドレーン領域を覆う二
酸化ケイ＊ＷＸＪにコンタクトホールを開孔後、およそ
０．８μｍの厚さのアルミニウムｆｔ真空蒸着シ、コれ
を・苧ター二／グ形成したものである。FIG. 4 shows that after the laser beam irradiation, the source, drain and y
- Each of the electrodes 9 to 1 has a diameter of approximately 0.8 μm after opening a contact hole in the silicon dioxide*WXJ covering the source and drain regions. It is made by vacuum evaporation of aluminum to a thickness of ft.
本実施例のＭＯＳＦＥＴの特性は、しきい値電圧（Ｖｔ
）は＄’！−ｔ２．５Ｖ、実効移動度（ｐａｒｔ ）
Ｆｉおよそ１６ｃｒＦ？／ｖ・■ｃで６った。The characteristics of the MOSFET of this example are as follows: threshold voltage (Vt
) is $'! -t2.5V, effective mobility (part)
Fi approximately 16crF? /v・■c got 6.
上記実施例では、非晶質基板として、プラス板を例にし
たが、種々のセラミ、クス板、そして個々の絶縁膜、が
堆積された単結晶シリコン板を基板として用いても同等
の結果が得られる。In the above example, a plastic plate was used as an example of the amorphous substrate, but the same results can be obtained by using a single crystal silicon plate on which various ceramics, ceramic plates, and individual insulating films are deposited as the substrate. can get.
レーデ−光照射時に、非晶質基板の温度を４００℃程度
まで上げることは、シリコン薄膜の結晶成長をよシ促進
する上で好ましい。It is preferable to raise the temperature of the amorphous substrate to about 400° C. during radar light irradiation in order to promote crystal growth of the silicon thin film.
また、レーデ−光の代りに、１子線、Ｘｓフラッシスラ
ングなど、他のエネルギービーム照射等によっても上記
実施例と同等の効果が得られる。Further, instead of the radar beam, the same effect as in the above embodiment can be obtained by using other energy beam irradiation such as a single beam or an Xs flash slung beam.
本発明は、ＦＥＴのみならず、・ンイバーラトランノス
タの製造にも勿論適用出来る。The present invention can of course be applied not only to the production of FETs but also to the production of universal transistors.
第１図〜第４図は本発明の一実施例のＭＤＳＦＥＴ製造
工程を示す図である。
１・・・非晶質基板（プラス）、２・・・シリコン４領
域、７・・・ドレイン領域、８・・・レーデ−光、９゜
１０．１１・・・電極。
出願人代理人 弁理士 鈴 江 武 彦第１
第２
第３
＝べ
／７1 to 4 are diagrams showing the manufacturing process of an MDSFET according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Amorphous substrate (plus), 2... Silicon 4 region, 7... Drain region, 8... Radar light, 9°10.11... Electrode. Applicant's agent Patent attorney Takehiko Suzue 1st 2nd 3rd = B/7
Claims (1)
て薄膜半導体装置を製造するに際して、島状シリコン領
域を形成した後、この島状シリコン領域を含む基板全面
を絶縁膜で被覆し、次いでこの絶縁膜を通して前記島状
シリコン領域に選択的に不純物をイオン注入した鏝、前
記島状シリコン領域にエネルギービームを照射してシリ
コンの結晶粒径の増大化とイオン注入不純物の電気的活
性化を同時に行うようにしたことを特徴とする薄膜半導
体装置の製造方法。When manufacturing a thin film semiconductor device using a silicon thin film deposited on a substrate as an active region, after forming an island-like silicon region, the entire surface of the substrate including the island-like silicon region is covered with an insulating film. A trowel is used to selectively implant impurity ions into the island-like silicon region through a film, and an energy beam is irradiated onto the island-like silicon region to simultaneously increase the silicon crystal grain size and electrically activate the ion-implanted impurity. A method for manufacturing a thin film semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9006782A JPS58206121A (en) | 1982-05-27 | 1982-05-27 | Manufacture of thin-film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9006782A JPS58206121A (en) | 1982-05-27 | 1982-05-27 | Manufacture of thin-film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58206121A true JPS58206121A (en) | 1983-12-01 |
Family
ID=13988192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9006782A Pending JPS58206121A (en) | 1982-05-27 | 1982-05-27 | Manufacture of thin-film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58206121A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242436A (en) * | 1985-08-19 | 1987-02-24 | Sony Corp | Manufacture of semiconductor device |
| JPS6295874A (en) * | 1985-10-23 | 1987-05-02 | Sony Corp | Manufacture of semiconductor device |
| JPS62299011A (en) * | 1986-06-18 | 1987-12-26 | Matsushita Electric Ind Co Ltd | Annealing of polycrystalline thin-film substrate |
| JPS6347980A (en) * | 1986-08-18 | 1988-02-29 | Fujitsu Ltd | Manufacture of thin film transistor |
| JPH02224255A (en) * | 1989-02-27 | 1990-09-06 | Hitachi Ltd | Thin film semiconductor device and manufacture thereof |
| JPH0442969A (en) * | 1990-06-06 | 1992-02-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| WO1994000882A1 (en) * | 1992-06-24 | 1994-01-06 | Seiko Epson Corporation | Thin film transistor, solid-state device, display device, and method for manufacturing thin film transistor |
| JPH0697443A (en) * | 1991-07-12 | 1994-04-08 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JPH06291316A (en) * | 1992-02-25 | 1994-10-18 | Semiconductor Energy Lab Co Ltd | Thin film insulated gate semiconductor device and manufacture thereof |
| JPH0758342A (en) * | 1994-07-11 | 1995-03-03 | Sony Corp | Production of thin-film transistor |
| US5397718A (en) * | 1992-02-21 | 1995-03-14 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing thin film transistor |
| US5894151A (en) * | 1992-02-25 | 1999-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having reduced leakage current |
| US5942768A (en) * | 1994-10-07 | 1999-08-24 | Semionductor Energy Laboratory Co., Ltd. | Semiconductor device having improved crystal orientation |
| JP2000004026A (en) * | 1999-06-02 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | Manufacture of mis-type semiconductor device |
| US6028333A (en) * | 1991-02-16 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US6221701B1 (en) * | 1984-05-18 | 2001-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and its manufacturing method |
| US6417543B1 (en) | 1993-01-18 | 2002-07-09 | Semiconductor Energy Laboratory Co., Ltd. | MIS semiconductor device with sloped gate, source, and drain regions |
| US6709907B1 (en) | 1992-02-25 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
| JP2006019527A (en) * | 2004-07-01 | 2006-01-19 | Dainippon Printing Co Ltd | Manufacturing method for polycrystalline silicon thin film, manufacturing method for thin film transistor, and substrate with silicon thin film |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5688317A (en) * | 1979-12-20 | 1981-07-17 | Fujitsu Ltd | Manufacture of semiconductor device |
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1982
- 1982-05-27 JP JP9006782A patent/JPS58206121A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5688317A (en) * | 1979-12-20 | 1981-07-17 | Fujitsu Ltd | Manufacture of semiconductor device |
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| US6660574B1 (en) | 1984-05-18 | 2003-12-09 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming a semiconductor device including recombination center neutralizer |
| US6221701B1 (en) * | 1984-05-18 | 2001-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Insulated gate field effect transistor and its manufacturing method |
| JPS6242436A (en) * | 1985-08-19 | 1987-02-24 | Sony Corp | Manufacture of semiconductor device |
| JPS6295874A (en) * | 1985-10-23 | 1987-05-02 | Sony Corp | Manufacture of semiconductor device |
| JPS62299011A (en) * | 1986-06-18 | 1987-12-26 | Matsushita Electric Ind Co Ltd | Annealing of polycrystalline thin-film substrate |
| JPS6347980A (en) * | 1986-08-18 | 1988-02-29 | Fujitsu Ltd | Manufacture of thin film transistor |
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| KR100309934B1 (en) * | 1992-06-24 | 2002-06-20 | 구사마 사부로 | Method of manufacturing thin film transistor, solid state device, display device, and thin film transistor |
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| US6627487B2 (en) | 1994-10-07 | 2003-09-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
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| JP2000004026A (en) * | 1999-06-02 | 2000-01-07 | Semiconductor Energy Lab Co Ltd | Manufacture of mis-type semiconductor device |
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