JPS6347980A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS6347980A JPS6347980A JP19169186A JP19169186A JPS6347980A JP S6347980 A JPS6347980 A JP S6347980A JP 19169186 A JP19169186 A JP 19169186A JP 19169186 A JP19169186 A JP 19169186A JP S6347980 A JPS6347980 A JP S6347980A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor layer
- film transistor
- insulating film
- activated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 14
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000010894 electron beam technology Methods 0.000 claims abstract description 7
- 230000008018 melting Effects 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 7
- 230000003213 activating effect Effects 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 229910018487 Ni—Cr Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
薄膜トランジスタの製造方法であって、基板上に形成さ
れた多結晶シリコン又は非晶質シリコンの半導体層のゲ
ート絶縁膜側の一部を光照射あるいは局所加熱により融
解し活性化させ、活性化領域と非活性化領域の２層構成
とすることにより、高速で動作でき且つオフ電流の低い
薄膜トランジスタを低温で製造することを可能とする。[Detailed Description of the Invention] [Summary] A method for manufacturing a thin film transistor, the method comprising: irradiating light or locally heating a portion of a semiconductor layer of polycrystalline silicon or amorphous silicon formed on a substrate on the gate insulating film side. By melting and activating it to form a two-layer structure of an activated region and a non-activated region, it is possible to manufacture a thin film transistor that can operate at high speed and has a low off-state current at a low temperature.
本発明は薄膜トランジスタの製造方法に関するもので、
さらに詳しく言えば高速かつオフ電流の低い薄膜トラン
ジスタを低温で作製できるｇＪ朦トランジスタの製造方
法に関するものである。The present invention relates to a method for manufacturing a thin film transistor,
More specifically, the present invention relates to a method for manufacturing a gJ thin film transistor, which enables high-speed thin film transistors with low off-state current to be manufactured at low temperatures.
従来の薄膜トランジスタとしては非晶質−シリコン薄膜
トランジスタが知られている。この非晶質薄膜トランジ
スタは大面積に低温で形成可能なことから液晶表示用ア
クティブ・マトリックス・スイッチに用いられるが電界
効果移動度が高々ｌ ｃｄ／ｓＶと小さいため大面積デ
バイスの駆動回路に要求される動作周波数（＞ＩＭＨｚ
）が得られない。このため大面積に形成可能で且つ高速
動作のできる薄膜トランジスタが要望されている。この
ため多結晶シリコンの半導体層をレーザを用いて活性化
させた薄膜トランジスタが開発されている。Amorphous-silicon thin film transistors are known as conventional thin film transistors. This amorphous thin film transistor is used in active matrix switches for liquid crystal displays because it can be formed over a large area at low temperatures, but because its field effect mobility is small at most l cd/sV, it is not required for drive circuits for large area devices. operating frequency (>IMHz
) is not obtained. Therefore, there is a demand for a thin film transistor that can be formed in a large area and can operate at high speed. For this reason, thin film transistors have been developed in which a polycrystalline silicon semiconductor layer is activated using a laser.
第３図は上記の多結晶シリコン半導体層をレーザを用い
て活性化させる薄膜トランジスタの製造方法を示す図で
ある。この方法は先ずａ図の如く基板１の上に絶縁膜２
及び多結晶シリコン又は非晶質シリコンの半導体層３を
形成し、この半導体層３にレーザ光４を照射して活性化
させる。次にｂ図の如くソース電極５及びドレイン電極
６を形成し、その上にゲート絶縁膜７を形成し、最後に
０図の如くゲート電極８及びソースドレイン電極からの
引出し電極５ａ 、６ａを形成するのである。FIG. 3 is a diagram showing a method for manufacturing a thin film transistor in which the above polycrystalline silicon semiconductor layer is activated using a laser. In this method, first, as shown in figure a, an insulating film 2 is placed on a substrate 1.
Then, a semiconductor layer 3 of polycrystalline silicon or amorphous silicon is formed, and this semiconductor layer 3 is irradiated with laser light 4 to activate it. Next, as shown in figure b, a source electrode 5 and a drain electrode 6 are formed, a gate insulating film 7 is formed thereon, and finally a gate electrode 8 and lead-out electrodes 5a and 6a from the source and drain electrodes are formed as shown in figure 0. That's what I do.
上記従来の製造方法では薄膜トランジスタを大面積に低
温で形成可能であるが第３図すに示す工程で結晶粒界が
全領域に広がり粒界で電流経路が形成され、オフ電流の
増大を招くという欠点がある。With the conventional manufacturing method described above, thin film transistors can be formed over a large area at low temperatures, but in the process shown in Figure 3, grain boundaries spread over the entire area and current paths are formed at the grain boundaries, leading to an increase in off-state current. There are drawbacks.
本発明はこのような点に鑑みて創作されたもので、大面
積に形成可能で且つ高速動作ができ、さらにオフ電流の
少ない薄膜トランジスタを作製可能な製造方法を提供す
ることを目的としている。The present invention was created in view of the above points, and an object of the present invention is to provide a manufacturing method capable of manufacturing a thin film transistor that can be formed in a large area, can operate at high speed, and has low off-state current.
このため本発明においては、ソース電極Ｓ及びドレイン
電極りが形成された絶縁基板１０上に多結晶シリコン又
は非晶質シリコンの半導体層１５を形成する工程と、前
記半導体層１５の一部を光照射あるいは局所加熱により
融解し活性化させ、活性領域１５ｂと非活性領域１５ａ
の２層構成とする工程とを含むことを特徴としている。Therefore, in the present invention, there is a step of forming a semiconductor layer 15 of polycrystalline silicon or amorphous silicon on the insulating substrate 10 on which the source electrode S and the drain electrode S are formed, and a part of the semiconductor layer 15 is exposed to light. The active region 15b and the non-active region 15a are melted and activated by irradiation or local heating.
The method is characterized in that it includes a step of forming a two-layer structure.
光照射あるいは局所加熱により多結晶シリコン又は非晶
質シリコンの一部を活性化させて活性化領域と非活性化
領域の２層構造とすることにより低温での作製が可能と
なり、且つ非活性領域の高抵抗によりオフ電流の抑制が
可能となる。By activating a part of polycrystalline silicon or amorphous silicon by light irradiation or local heating to form a two-layer structure of an activated region and a non-activated region, it is possible to fabricate at a low temperature. The high resistance makes it possible to suppress off-state current.
第１図は本発明の実施例の薄膜トランジスタの製造方法
を説明するための図であり、３−％−ｇはその工程説明
図である。FIG. 1 is a diagram for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention, and 3-%-g is an explanatory diagram of the process.
本実施例の方法は、先ずａ図に示すようにガラス等の絶
縁基＋ＪｉｌＯ上にプラズマＣＶＤ法、光ＣＶＤ法また
はスパッタ法により絶縁膜１１を形成する。絶縁膜１１
には酸化シリコン膜、あるいは窒化シリコン膜または酸
窒化シリコン膜を用い膜厚は５００〜１０００人が望ま
しい。次にｂ図の如く下部電極膜１２を形成し、その上
にプラズマＣＶＤ法またはスパッタ法により不純物をド
ーピングした多結晶シリコンまたは非晶質シリコン１３
を〜３００人堆積する。不純物としてはＰ、Ｂ等が用い
られる。また下部電極膜としてはＣｒ、Ｔｉ。In the method of this embodiment, first, as shown in Figure a, an insulating film 11 is formed on an insulating substrate such as glass+JilO by plasma CVD, photoCVD, or sputtering. Insulating film 11
A silicon oxide film, a silicon nitride film, or a silicon oxynitride film is preferably used for the film, and the film thickness is preferably 500 to 1000. Next, as shown in figure b, a lower electrode film 12 is formed, and polycrystalline silicon or amorphous silicon 13 doped with impurities by plasma CVD or sputtering is formed thereon.
Deposit ~300 people. P, B, etc. are used as impurities. Further, the lower electrode film is made of Cr or Ti.
Ｎｉ−Ｃｒ 、 Ａβ、ＩＴＯ等が用いられる。その
後Ｃ図のように通常のホトリソグラフィを用い下部電極
膜１２とシリコン膜１３からソース電極Ｓとドレイン電
極りを形成し、然る後にソース電極Ｓ及びドレイン電極
りの多結晶シリコンまたは非晶質シリコン１３をレーザ
又は電子線１４の照射により融解活性化させる。次にｄ
図の如く半導体層１５として多結晶シリコンまたは非晶
シリコンを１０００〜３０００人の厚さにプラズマＣＶ
Ｄ法またはスパッタ法または光ＣＶＤ法により堆積し、
次いでｅ図の如く通常のホトリソグラフィを用いてパタ
ーン形成後レーザ又は電子線１４の照射または赤外線ヒ
ータの局所加熱法によりゲート絶縁膜側の一部、即ちソ
ース・ドレイン電極Ｓ、Ｄの反対側の一部（厚さ５００
人〜１５００人）を融解活性化させ、結晶粒を成長させ
、活性領域１５ｂを形成する。ソース・ドレイン電極側
には活性化しない領域１５ａが残り、核部は高抵抗のま
まである。なお活性化領域形成の制御は、レーザを用い
る場合は励起光源と波長と半導体層の吸収係数の関係に
より所望の領域のみ活性化でき、電子ビームの場合はエ
ネルギーと走査時間により活性化領域を制御できる。Ni-Cr, Aβ, ITO, etc. are used. Thereafter, as shown in Figure C, a source electrode S and a drain electrode are formed from the lower electrode film 12 and the silicon film 13 using ordinary photolithography, and then polycrystalline silicon or amorphous silicon is formed for the source electrode S and the drain electrode. The silicon 13 is melted and activated by laser or electron beam 14 irradiation. then d
As shown in the figure, polycrystalline silicon or amorphous silicon is formed by plasma CVD to a thickness of 1000 to 3000 layers as the semiconductor layer 15.
Deposited by D method, sputtering method or photo CVD method,
Next, as shown in figure e, after forming a pattern using normal photolithography, a part of the gate insulating film side, that is, the opposite side of the source/drain electrodes S and D, is formed by irradiation with a laser or electron beam 14 or by local heating with an infrared heater. Part (thickness 500
(~1500 people) is melted and activated to grow crystal grains and form the active region 15b. An unactivated region 15a remains on the source/drain electrode side, and the core remains at high resistance. Note that when using a laser, only the desired region can be activated by the relationship between the excitation light source, wavelength, and absorption coefficient of the semiconductor layer, and when using an electron beam, the activation region can be controlled by energy and scanning time. can.
次にｆ図の如くゲート絶縁膜１６をプラズマＣＶＤ法、
または光ＣＶＤ法、あるいはスパッタ法により厚さ３０
００人〜５０００人堆積する。ゲート絶縁膜１６として
は酸化シリコン膜、窒化シリコン膜、あるいは酸窒化シ
リコン膜のいずれか、またはこれらの膜からなる多層膜
を用いる。次いでゲート電極１７をスパッタ法または電
子ビーム蒸着法により厚さ１０００〜２０００人に堆積
しパターン形成する。最後にｇ図の如くソース電極Ｓ及
びドレイン電極り上のゲート絶縁膜１６にスルーホール
を形成し、金属電極１８ 、１９をスパッタ法あるいは
電子ビーム蒸着法により成膜後パターン形成する。Next, as shown in figure f, the gate insulating film 16 is formed by plasma CVD.
Or, the thickness is 30 mm by photo-CVD method or sputtering method.
00 to 5000 people will accumulate. As the gate insulating film 16, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a multilayer film made of these films is used. Next, a gate electrode 17 is deposited to a thickness of 1,000 to 2,000 wafers by sputtering or electron beam evaporation to form a pattern. Finally, as shown in figure g, through holes are formed in the gate insulating film 16 above the source electrode S and drain electrode, and metal electrodes 18 and 19 are formed and patterned by sputtering or electron beam evaporation.
ゲート電極１７およびソース・ドレインの金属電極１８
、１９にはＡＪ 、 Ｎｉ−Ｃｒ 、 Ｃｒ 、
Ｔｉ 、 Ｍｏ 。Gate electrode 17 and source/drain metal electrodes 18
, 19 has AJ, Ni-Cr, Cr,
Ti, Mo.
Ｔａ、ＩＴＯ等が用いられる。Ta, ITO, etc. are used.
本実施例はこのようにして低温で薄膜トランジスタを製
造することができる。また本実施例方法により作製され
た薄膜トランジスタは高速動作ができ、且つ多結晶シリ
コン又は非結晶シリコンの半導体、［１５のソース・ド
レイン電極Ｓ、Ｄ側に高抵抗の非活性層１５ａが残って
いるためオフ電流が小さい。In this embodiment, thin film transistors can be manufactured at low temperatures in this manner. Further, the thin film transistor manufactured by the method of this embodiment can operate at high speed, and is made of a polycrystalline silicon or amorphous silicon semiconductor, and has a high resistance inactive layer 15a remaining on the source/drain electrodes S and D side of [15]. Therefore, the off-state current is small.
第２図は本発明の他の実施例を説明するための図であり
、ａ−ｆはその工程説明図である。同図において第１図
と同一部分は同一符号を付して示した。FIG. 2 is a diagram for explaining another embodiment of the present invention, and a to f are diagrams for explaining the process. In this figure, the same parts as in FIG. 1 are designated by the same reference numerals.
本実施例が前実施例と異なるところは、第１図のｅ工程
で行なった半導体１Ｊ１５のゲート絶縁膜側の融解を第
２図ｅの如くゲート絶縁膜堆積後に行なうことである。This embodiment differs from the previous embodiment in that the melting of the gate insulating film side of the semiconductor 1J15 performed in step e of FIG. 1 is performed after the gate insulating film is deposited as shown in FIG. 2e.
本実施例によれば半導体層１５とゲート絶縁膜１６を連
続して堆積することができるので、該界面に生ずる準位
を１０１′ｃＩｎ−２まで減小できる。従ってしきい値
電圧のばらつきのない製品が得られる。また半導体層Ｉ
５に接する側のゲート絶縁膜１６中に存在する水素が半
導体層融解の際に生ずる結晶粒界のダングリングボンド
を水素化し、従って電界効果移動度のより大なる薄膜ト
ランジスタを得ることができる。According to this embodiment, since the semiconductor layer 15 and the gate insulating film 16 can be deposited successively, the level generated at the interface can be reduced to 101'cIn-2. Therefore, a product without variations in threshold voltage can be obtained. Also, the semiconductor layer I
Hydrogen present in the gate insulating film 16 on the side contacting the semiconductor layer hydrogenates the dangling bonds at the crystal grain boundaries that are generated when the semiconductor layer is melted, thus making it possible to obtain a thin film transistor with higher field effect mobility.
なお以上の実施例は薄膜トランジスタを用いて説明した
が、三次元回路用Ｓｏｌ技術にも適用できる。また半導
体層に混入する不純物及び濃度によりｎチャンネル、ｐ
チャンネルのいずれでも形成可能である。Although the above embodiments have been explained using thin film transistors, they can also be applied to Sol technology for three-dimensional circuits. Also, depending on the impurity and concentration mixed into the semiconductor layer, n-channel, p-channel
Any channel can be formed.
以上述べてきたように本発明によれば、半導体層の一部
をレーザ、電子線等の照射又は赤外線ヒータによる局所
加熱により活性化させることによりオフ電流の少ない薄
膜トランジスタを低温で作製でき、実用的には極めて有
用である。As described above, according to the present invention, thin film transistors with low off-state current can be fabricated at low temperatures by activating a part of the semiconductor layer by irradiation with a laser, electron beam, etc. or local heating with an infrared heater, which is practical. It is extremely useful.
第１図は本発明の詳細な説明するための図、第２図は本
発明の他の実施例を説明するだめの図、
第３図は従来の薄膜トランジスタの装造方法を説明する
ための図である。
第１図、第２図において、
１０は基板、
１１は絶縁膜、
１２は下部電極膜、
１３は不純物をドープしたシリコン膜、１４はレーザ又
は電子線、
１５は多結晶シリコン又は非晶質シリコンの半導体層、
１５ａは半導体層の非活性領域、
１５ｂは半導体層の活性領域、
１６はゲート絶縁膜、
１７はゲート電極、
１８ 、１９は金属電極、
Ｓはソース電極、
Ｄはドレイン電極である。FIG. 1 is a diagram for explaining the present invention in detail, FIG. 2 is a diagram for explaining another embodiment of the present invention, and FIG. 3 is a diagram for explaining a conventional method of manufacturing a thin film transistor. It is. 1 and 2, 10 is a substrate, 11 is an insulating film, 12 is a lower electrode film, 13 is a silicon film doped with impurities, 14 is a laser or an electron beam, and 15 is polycrystalline silicon or amorphous silicon 15a is a non-active region of the semiconductor layer, 15b is an active region of the semiconductor layer, 16 is a gate insulating film, 17 is a gate electrode, 18 and 19 are metal electrodes, S is a source electrode, and D is a drain electrode. .
Claims (1)
れた絶縁基板（１０）上に多結晶シリコン又は非晶質シ
リコンの半導体層（１５）を形成する工程と、 上記半導体層（１５）の一部を光照射あるいは局所加熱
により融解し活性化させ、活性領域（１５ｂ）と非活性
領域（１５ａ）の２層構成とする工程とを含む薄膜トラ
ンジスタの製造方法。 ２、上記融解手段が電子線、レーザ、赤外線ヒータであ
ることを特徴とする特許請求の範囲第１項記載の薄膜ト
ランジスタの製造方法。 ３、上記融解の際、半導体層（１５）がパターン形成さ
れた後、融解を行なうことを特徴とする特許請求の範囲
第１項記載の薄膜トランジスタの製造方法。 ４、上記融解の際、ゲート絶縁膜（１６）の堆積後に融
解を行なうことを特徴とする特許請求の範囲第１項記載
の薄膜トランジスタの製造方法。[Claims] 1. Forming a semiconductor layer (15) of polycrystalline silicon or amorphous silicon on an insulating substrate (10) on which a source electrode (S) and a drain electrode (D) are formed; A method for manufacturing a thin film transistor, comprising the step of melting and activating a part of the semiconductor layer (15) by light irradiation or local heating to form a two-layer structure of an active region (15b) and an inactive region (15a). 2. The method for manufacturing a thin film transistor according to claim 1, wherein the melting means is an electron beam, a laser, or an infrared heater. 3. The method for manufacturing a thin film transistor according to claim 1, wherein the melting is performed after the semiconductor layer (15) has been patterned. 4. The method for manufacturing a thin film transistor according to claim 1, wherein the melting is performed after the gate insulating film (16) is deposited.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61191691A JP2735177B2 (en) | 1986-08-18 | 1986-08-18 | Thin film transistor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61191691A JP2735177B2 (en) | 1986-08-18 | 1986-08-18 | Thin film transistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6347980A true JPS6347980A (en) | 1988-02-29 |
| JP2735177B2 JP2735177B2 (en) | 1998-04-02 |
Family
ID=16278856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61191691A Expired - Fee Related JP2735177B2 (en) | 1986-08-18 | 1986-08-18 | Thin film transistor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2735177B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0312637A (en) * | 1989-06-12 | 1991-01-21 | Matsushita Electron Corp | Manufacture of image display device |
| JPH0335535A (en) * | 1989-06-30 | 1991-02-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin film field effect transistor |
| US5208187A (en) * | 1990-07-06 | 1993-05-04 | Tsubochi Kazuo | Metal film forming method |
| JPH06342909A (en) * | 1990-08-29 | 1994-12-13 | Internatl Business Mach Corp <Ibm> | Thin-film transistor and its manufacture |
| JPH09501509A (en) * | 1993-07-29 | 1997-02-10 | ハネウエル・インコーポレーテッド | Silicon pixel electrode |
| US7094656B2 (en) * | 2003-10-07 | 2006-08-22 | Industrial Technology Research Institute | Method of forming poly-silicon thin film transistors |
| WO2011141948A1 (en) * | 2010-05-10 | 2011-11-17 | パナソニック株式会社 | Thin film transistor device and method for manufacturing thin film transistor device |
| US11362215B2 (en) * | 2018-03-30 | 2022-06-14 | Intel Corporation | Top-gate doped thin film transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58206121A (en) * | 1982-05-27 | 1983-12-01 | Toshiba Corp | Manufacture of thin-film semiconductor device |
| JPS60109282A (en) * | 1983-11-17 | 1985-06-14 | Seiko Epson Corp | Semiconductor device |
-
1986
- 1986-08-18 JP JP61191691A patent/JP2735177B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58206121A (en) * | 1982-05-27 | 1983-12-01 | Toshiba Corp | Manufacture of thin-film semiconductor device |
| JPS60109282A (en) * | 1983-11-17 | 1985-06-14 | Seiko Epson Corp | Semiconductor device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0312637A (en) * | 1989-06-12 | 1991-01-21 | Matsushita Electron Corp | Manufacture of image display device |
| JPH0335535A (en) * | 1989-06-30 | 1991-02-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin film field effect transistor |
| US5208187A (en) * | 1990-07-06 | 1993-05-04 | Tsubochi Kazuo | Metal film forming method |
| JPH06342909A (en) * | 1990-08-29 | 1994-12-13 | Internatl Business Mach Corp <Ibm> | Thin-film transistor and its manufacture |
| JPH09501509A (en) * | 1993-07-29 | 1997-02-10 | ハネウエル・インコーポレーテッド | Silicon pixel electrode |
| US7094656B2 (en) * | 2003-10-07 | 2006-08-22 | Industrial Technology Research Institute | Method of forming poly-silicon thin film transistors |
| US7361566B2 (en) | 2003-10-07 | 2008-04-22 | Industrial Technology Research Institute | Method of forming poly-silicon thin film transistors |
| WO2011141948A1 (en) * | 2010-05-10 | 2011-11-17 | パナソニック株式会社 | Thin film transistor device and method for manufacturing thin film transistor device |
| US11362215B2 (en) * | 2018-03-30 | 2022-06-14 | Intel Corporation | Top-gate doped thin film transistor |
| US11862730B2 (en) | 2018-03-30 | 2024-01-02 | Intel Corporation | Top-gate doped thin film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2735177B2 (en) | 1998-04-02 |
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