JP2735177B2 - Thin film transistor and method of manufacturing the same - Google Patents
Thin film transistor and method of manufacturing the sameInfo
- Publication number
- JP2735177B2 JP2735177B2 JP61191691A JP19169186A JP2735177B2 JP 2735177 B2 JP2735177 B2 JP 2735177B2 JP 61191691 A JP61191691 A JP 61191691A JP 19169186 A JP19169186 A JP 19169186A JP 2735177 B2 JP2735177 B2 JP 2735177B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- electrode
- thin film
- insulating film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010408 film Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000003213 activating effect Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 229910018487 Ni—Cr Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- -1 C r Substances 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Description
【発明の詳細な説明】
〔概 要〕
薄膜トランジスタ及びその製造方法であって、基板上
に形成された多結晶シリコン又は非晶質シリコンの半導
体層のゲート絶縁膜側の一部を光照射あるいは局所加熱
により融解し活性化させ、活性化領域と非活性化領域の
２層構成とすることにより、高速で動作でき且つオフ電
流の低い薄膜トランジスタを低温で製造することを可能
とする。
〔産業上の利用分野〕
本発明は薄膜トランジスタ及びその製造方法に関する
もので、さらに詳しく言えば高速かつオフ電流の低い薄
膜トランジスタを低温で作製できる薄膜トランジスタ及
びその製造方法に関するものである。
従来の薄膜トランジスタとしては非晶質シリコン薄膜
トランジスタが知られている。この非晶質薄膜トランジ
スタは第面積に低温で形成可能なことから液晶表示用ア
クティブ・マトリックス・スイッチに用いられるが電界
効果移動度が高々1cm2/sVと小さいため大面積デバイス
の駆動回路に要求される動作周波数（＞1MHz）が得られ
ない。このため大面積に形成可能で且つ高速動作のでき
る薄膜トランジスタが要望されている。このため多結晶
シリコンの半導体層をレーザを用いて活性化させた薄膜
トランジスタが開発されている。
〔従来の技術〕
第３図は上記の多結晶シリコン半導体層をレーザを用
いて活性化させる薄膜トランジスタの製造方法を示す図
である。この方法は先ずａ図の如く基板１の上に絶縁膜
２及び多結晶シリコン又は非晶質シリコンの半導体層３
を形成し、この半導体層３にレーザ光４を照射して活性
化させる。次にｂ図の如くソース電極５及びドレイン電
極６を形成し、その上にゲート絶縁膜７を形成し、最後
にＣ図の如くゲート電極８及びソースドレイン電極から
の引出し電極5a,6aを形成するのである。
〔発明が解決しようとする問題点〕
上記従来の製造方法では薄膜トランジスタを大面積に
低温で形成可能であるが第３図ｂに示す工程で結晶粒界
が全領域に広がり粒界で電流経路が形成され、オフ電流
の増大を招くという欠点がある。
本発明はこのような点に鑑みて創作されたもので、大
面積に形成可能で且つ高速動作ができ、さらにオフ電流
の少ない薄膜トランジスタを作製可能な製造方法を提供
することを目的としている。
〔問題点を解決するための手段〕
このため本発明の薄膜トランジスタの製造方法におい
ては、ソース電極Ｓ及びドレイン電極Ｄが形成された絶
縁基板10上に多結晶シリコン又は非晶質シリコンの半導
体層15を形成する工程と、上記半導体層15の一部を光照
射あるいは局所加熱により融解し活性化させ、上記半導
体層の上層となる活性領域15bと、上記半導体層の下層
となり上記ソース電極Ｓ及びドレイン電極Ｄと接する非
活性領域15aの２層構成とする工程と、上記活性領域15b
上にゲート絶縁膜16を介してゲート電極17を形成する工
程とを含むことを特徴としている。
また、本発明の薄膜トランジスタにおいては、絶縁基
板10と、絶縁基板10上に形成されたソース電極Ｓ及びド
レイン電極Ｄと、ソース電極Ｓ及びドレイン電極Ｄに接
して設けられた半導体層15と、半導体層15上にゲート絶
縁膜16を介して形成されたゲート電極Ｄとを備え、上記
半導体層15は、下層の非活性領域15a及び上層の活性領
域15bの２層構造からなり、上記非活性領域15aが上記ソ
ース電極Ｓ及びドレイン電極Ｄと接し、さらに、上記活
性領域15bが上記ゲート絶縁膜16と接していることを特
徴としている。
〔作 用〕
光照射あるいは局所加熱により多結晶シリコン又は非
晶質シリコンの一部を活性化させて活性化領域と非活性
化領域の２層構造とすることにより低温での作製が可能
となり、且つ非活性領域の高抵抗によりオフ電流の抑制
が可能となる。
〔実施例〕
第１図は本発明の実施例の薄膜トランジスタの製造方
法を説明するための図であり、ａ〜ｇはその工程説明図
である。
本実施例の方法は、先ずａ図に示すようにガラス等の
絶縁基板10上にプラズマCVD法、光CVD法またはスパッタ
法により絶縁膜11を形成する。絶縁膜11には酸化シリコ
ン膜、あるいは窒化シリコン膜または酸窒化シリコン膜
を用い膜厚は500〜1000Åが望ましい。次にｂ図の如く
下部電極膜12を形成し、その上にプラズマCVD法または
スパッタ法により不純物をドーピングした多結晶シリコ
ンまたは非晶質シリコン13を〜300Å堆積する。不純物
としてはP,B等が用いられる。また下部電極膜としてはC
r,Ti,Ni−Cr,Al,ITO等が用いられる。その後Ｃ図のよう
に通常のホトリソグラフィを用い下部電極膜12とシリコ
ン膜13からソース電極Ｓとドレイン電極Ｄを形成し、然
る後にソース電極Ｓ及びドレイン電極Ｄの多結晶シリコ
ンまたは非晶質シリコン13をレーザ又は電子線14の照射
により融解活性化させる。次にｄ図の如く半導体層15と
して多結晶シリコンまたは非晶質シリコンを1000〜3000
Åの厚さにプラズマCVD法またはスパッタ法または光CVD
法により堆積し、次いでｅ図の如く通常のホトリソグラ
フィを用いてパターン形成後レーザ又は電子線14の照射
または赤外線ヒータの局所加熱法によりゲート絶縁膜側
の一部、即ちソース・ドレイン電極S,Dの反対側の一部
（厚さ500Å〜1500Å）を融解活性化させ、結晶粒を成
長させ、活性領域15bを形成する。ソース・ドレイン電
極側には活性化しない領域15aが残り、該部は高抵抗の
ままである。なお活性化領域形成の制御は、レーザを用
いる場合は励起光源と波長と半導体層の吸収係数の関係
により所望の領域のみ活性化でき、電子ビームの場合は
エネルギーと走査時間により活性化領域を制御できる。
次にｆ図の如くゲート絶縁膜16をプラズマCVD法、ま
たは光CVD法、あるいはスパッタ法により厚さ3000Å〜5
000Å堆積する。ゲート絶縁膜16としては酸化シリコン
膜、窒化シリコン膜、あるいは酸窒化シリコン膜のいず
れか、またはこれらの膜からなる多層膜を用いる。次い
でゲート電極17をスパッタ法または電子ビーム蒸着法に
より厚さ1000〜2000Åに堆積しパターン形成する。最後
にｇ図の如くソース電極Ｓ及びドレイン電極Ｄ上のゲー
ト絶縁膜16にスルーホールを形成し、金属電極18,19を
スパッタ法あるいは電子ビーム蒸着法により成膜後パタ
ーン形成する。ゲート電極17およびソース・ドレインの
金属電極18,19にはAl,Ni−Cr,Cr,Ti,Mo,Ta,ITO等が用い
られる。
本実施例はこのようにして低温で薄膜トランジスタを
製造することができる。また本実施例方法により作製さ
れた薄膜トランジスタは高速動作ができ、且つ多結晶シ
リコン又は非結晶シリコンの半導体層15のソース・ドレ
イン電極S,D側に高抵抗の非活性層15aが残っているため
オフ電流が小さい。
第２図は本発明の他の実施例を説明するための図であ
り、ａ〜ｆはその工程説明図である。同図において第１
図と同一部分は同一符号を付して示した。
本実施例が前実施例と異なるところは、第１図のｅ工
程で行なった半導体層15のゲート絶縁膜側の融解を第２
図ｅの如くゲート絶縁膜堆積後に行なうことである。
本実施例によれば半導体層15とゲート絶縁膜16を連続
して堆積することができるので、該界面に生ずる準位を
1010cm-2まで滅小できる。従ってしきい値電圧のばらつ
きのない製品が得られる。また半導体層15に接する側の
ゲート絶縁膜16中に存在する水素が半導体層融解の際に
生ずる結晶粒界のダングリングポッドを水素化し、従っ
て電界効果移動度のより大なる薄膜トランジスタを得る
ことができる。
なお以上の実施例は薄膜トランジスタを用いて説明し
たが、三次元回路用SOI技術にも適用できる。また半導
体層に混入する不純物及び濃度によりｎチャンネル、ｐ
チャンネルのいずれでも形成可能である。
〔発明の効果〕
以上述べてきたように本発明によれば、半導体層の一
部をレーザ、電子線等の照射又は赤外線ヒータによる局
所加熱により活性化させることによりオフ電流の少ない
薄膜トランジスタを低温で作製でき、実用的には極めて
有用である。The present invention relates to a thin film transistor and a method for manufacturing the same, wherein a part of a polycrystalline silicon or amorphous silicon semiconductor layer formed on a substrate on a gate insulating film side is irradiated with light or locally. By melting and activating by heating to form a two-layer structure of an activated region and a non-activated region, a thin film transistor which can operate at high speed and has low off-state current can be manufactured at low temperature. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to a thin film transistor capable of producing a thin film transistor with high speed and low off current at a low temperature and a method for manufacturing the same. As a conventional thin film transistor, an amorphous silicon thin film transistor is known. Since this amorphous thin film transistor can be formed at a low temperature in the first area, it is used for an active matrix switch for liquid crystal display.However, since the field effect mobility is as small as 1 cm 2 / sV at most, it is required for a drive circuit of a large area device. Operating frequency (> 1MHz) cannot be obtained. For this reason, a thin film transistor which can be formed in a large area and can operate at high speed is demanded. For this reason, a thin film transistor in which a semiconductor layer of polycrystalline silicon is activated using a laser has been developed. [Prior Art] FIG. 3 shows a method of manufacturing a thin film transistor in which the above-mentioned polycrystalline silicon semiconductor layer is activated by using a laser. In this method, first, an insulating film 2 and a semiconductor layer 3 of polycrystalline silicon or amorphous silicon are formed on a substrate 1 as shown in FIG.
Is formed, and the semiconductor layer 3 is activated by irradiating the semiconductor layer 3 with a laser beam 4. Next, a source electrode 5 and a drain electrode 6 are formed as shown in Fig. B, a gate insulating film 7 is formed thereon, and finally, gate electrodes 8 and extraction electrodes 5a and 6a from the source and drain electrodes are formed as shown in Fig. C. You do it. [Problems to be Solved by the Invention] In the above-mentioned conventional manufacturing method, a thin film transistor can be formed over a large area at a low temperature. However, in the step shown in FIG. Formed, which causes an increase in off-state current. The present invention has been made in view of the above points, and has as its object to provide a manufacturing method capable of forming a thin film transistor which can be formed in a large area, can operate at high speed, and has a small off-state current. [Means for Solving the Problems] Therefore, in the method of manufacturing a thin film transistor of the present invention, the semiconductor layer 15 of polycrystalline silicon or amorphous silicon is formed on the insulating substrate 10 on which the source electrode S and the drain electrode D are formed. Forming a part of the semiconductor layer 15 by irradiating or irradiating a part of the semiconductor layer 15 by light irradiation or local heating, and activating the active region 15b to be the upper layer of the semiconductor layer and the source electrode S and the drain to be the lower layer of the semiconductor layer. A step of forming a two-layer structure of the non-active region 15a in contact with the electrode D;
Forming a gate electrode 17 thereover via a gate insulating film 16. Further, in the thin film transistor of the present invention, the insulating substrate 10, the source electrode S and the drain electrode D formed on the insulating substrate 10, the semiconductor layer 15 provided in contact with the source electrode S and the drain electrode D, A gate electrode D formed on a layer 15 with a gate insulating film 16 interposed therebetween, wherein the semiconductor layer 15 has a two-layer structure of a lower inactive region 15a and an upper active region 15b, 15a is in contact with the source electrode S and the drain electrode D, and the active region 15b is in contact with the gate insulating film 16. [Operation] By activating part of polycrystalline silicon or amorphous silicon by light irradiation or local heating to form a two-layer structure of an activated region and a non-activated region, fabrication at a low temperature becomes possible. In addition, off-state current can be suppressed by the high resistance of the inactive region. Embodiment FIG. 1 is a diagram for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention, and a to g are explanatory diagrams of the steps. In the method of the present embodiment, first, as shown in FIG. 1A, an insulating film 11 is formed on an insulating substrate 10 such as glass by a plasma CVD method, a photo CVD method or a sputtering method. As the insulating film 11, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is used, and its thickness is desirably 500 to 1000 mm. Next, as shown in FIG. 2B, a lower electrode film 12 is formed, and polycrystalline silicon or amorphous silicon 13 doped with impurities is deposited thereon by plasma CVD or sputtering to a thickness of about 300 DEG. P, B, etc. are used as impurities. Also, as the lower electrode film, C
r, Ti, Ni-Cr, Al, ITO, etc. are used. Thereafter, a source electrode S and a drain electrode D are formed from the lower electrode film 12 and the silicon film 13 by using ordinary photolithography as shown in FIG. The silicon 13 is melt-activated by irradiation with a laser or an electron beam 14. Next, as shown in FIG.
Plasma CVD method or sputtering method or optical CVD to a thickness of Å
Then, after pattern formation using ordinary photolithography as shown in Figure e, a part of the gate insulating film side, that is, source / drain electrodes S, by laser or electron beam irradiation or local heating using an infrared heater. A part on the opposite side of D (thickness: 500 to 1500) is melt-activated to grow crystal grains to form an active region 15b. A non-activated region 15a remains on the source / drain electrode side, and this portion remains at high resistance. In the case of using a laser, only the desired region can be activated by the relationship between the excitation light source, the wavelength, and the absorption coefficient of the semiconductor layer. In the case of an electron beam, the activation region is controlled by the energy and the scanning time. it can. Next, the gate insulating film 16 is formed to a thickness of 3000 to
000Å deposited. As the gate insulating film 16, any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a multilayer film including these films is used. Next, a gate electrode 17 is deposited to a thickness of 1000 to 2000 mm by sputtering or electron beam evaporation to form a pattern. Finally, through holes are formed in the gate insulating film 16 on the source electrode S and the drain electrode D as shown in FIG. 9G, and the metal electrodes 18 and 19 are formed by sputtering or electron beam evaporation and then patterned. For the gate electrode 17 and the source / drain metal electrodes 18, 19, Al, Ni-Cr, Cr, Ti, Mo, Ta, ITO, or the like is used. In this embodiment, a thin film transistor can be manufactured at a low temperature in this manner. In addition, the thin film transistor manufactured by the method of this embodiment can operate at high speed, and the high-resistance non-active layer 15a remains on the source / drain electrodes S and D sides of the semiconductor layer 15 of polycrystalline silicon or amorphous silicon. Low off current. FIG. 2 is a view for explaining another embodiment of the present invention, and a to f are explanatory views of the steps. In FIG.
The same parts as those in the drawing are denoted by the same reference numerals. This embodiment is different from the previous embodiment in that the melting of the semiconductor layer 15 on the side of the gate insulating film performed in the step e in FIG.
This is performed after the gate insulating film is deposited as shown in FIG. According to the present embodiment, since the semiconductor layer 15 and the gate insulating film 16 can be continuously deposited, the level generated at the interface can be reduced.
It can be reduced to 10 10 cm -2 . Therefore, a product without variation in threshold voltage can be obtained. Further, hydrogen present in the gate insulating film 16 on the side in contact with the semiconductor layer 15 hydrogenates the dangling pods at the crystal grain boundaries generated when the semiconductor layer is melted, so that a thin film transistor having higher field effect mobility can be obtained. it can. Although the above embodiments have been described using thin film transistors, the present invention can be applied to SOI technology for three-dimensional circuits. Further, depending on the impurity and concentration mixed in the semiconductor layer, n channel, p
Any of the channels can be formed. [Effects of the Invention] As described above, according to the present invention, a thin film transistor with low off-current can be formed at a low temperature by activating a part of a semiconductor layer by irradiation with a laser, an electron beam, or the like or local heating by an infrared heater. It can be manufactured and is extremely useful in practice.
【図面の簡単な説明】
第１図は本発明の実施例を説明するための図、
第２図は本発明の他の実施例を説明するための図、
第３図は従来の薄膜トランジスタの製造方法を説明する
ための図である。
第１図、第２図において、
10は基板、
11は絶縁膜、
12は下部電極膜、
13は不純物をドープしたシリコン膜、
14はレーザ又は電子線、
15は多結晶シリコン又は非晶質シリコンの半導体層、
15aは半導体層の非活性領域、
15bは半導体層の活性領域、
16はゲート絶縁膜、
17はゲート電極、
18,19は金属電極、
Ｓはソース電極、
Ｄはドレイン電極である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for explaining an embodiment of the present invention, FIG. 2 is a view for explaining another embodiment of the present invention, and FIG. It is a figure for explaining a method. 1 and 2, 10 is a substrate, 11 is an insulating film, 12 is a lower electrode film, 13 is a silicon film doped with impurities, 14 is a laser or electron beam, 15 is polycrystalline silicon or amorphous silicon. 15a is an inactive region of the semiconductor layer, 15b is an active region of the semiconductor layer, 16 is a gate insulating film, 17 is a gate electrode, 18 and 19 are metal electrodes, S is a source electrode, and D is a drain electrode. .
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山口 忠久 川崎市中原区上小田中1015番地 富士通 株式会社内 (56)参考文献 特開 昭62−141776（ＪＰ，Ａ) 特開 昭60−109282（ＪＰ，Ａ) 特開 昭58−206121（ＪＰ，Ａ) 特開 昭59−65882（ＪＰ，Ａ) 特開 昭59−44085（ＪＰ，Ａ) ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tadahisa Yamaguchi Fujitsu, 1015 Ueodanaka, Nakahara-ku, Kawasaki-shi Inside the corporation (56) References JP-A-62-141776 (JP, A) JP-A-60-109282 (JP, A) JP-A-58-206121 (JP, A) JP-A-59-65882 (JP, A) JP-A-59-44085 (JP, A)
Claims (1)
れた絶縁基板（10）上に多結晶シリコン又は非晶質シリ
コンの半導体層（15）を形成する工程と、 上記半導体層（15）の一部を光照射あるいは局所加熱に
より融解し活性化させ、上記半導体層の上層となる活性
領域（15b）と、上記半導体層の下層となり上記ソース
電極（Ｓ）及びドレイン電極（Ｄ）と接する非活性領域
（15a）の２層構成とする工程と、 上記活性領域（15b）上にゲート絶縁膜（16）を介して
ゲート電極（17）を形成する工程とを含むことを特徴と
する薄膜トランジスタの製造方法。 ２．上記融解手段が電子線、レーザ、赤外線ヒータであ
ることを特徴とする特許請求の範囲第１項記載の薄膜ト
ランジスタの製造方法。 ３．上記融解の際、半導体層（15）がパターン形成され
た後、融解を行なうことを特徴とする特許請求の範囲第
１項記載の薄膜トランジスタの製造方法。 ４．上記融解の際、ゲート絶縁膜（16）の堆積後に融解
を行なうことを特徴とする特許請求の範囲第１項記載の
薄膜トランジスタの製造方法。 ５．絶縁基板（10）と、絶縁基板（10）上に形成された
ソース電極（Ｓ）及びドレイン電極（Ｄ）と、ソース電
極（Ｓ）及びドレイン電極（Ｄ）に接して設けられた半
導体層（15）と、半導体層（15）上にゲート絶縁膜（1
6）を介して形成されたゲート電極（Ｄ）とを備え、 上記半導体層（15）は、下層の非活性領域（15a）及び
上層の溶融固化された活性領域（15b）の２層構造から
なり、上記非活性領域（15a）が上記ソース電極（Ｓ）
及びドレイン電極（Ｄ）と接し、さらに、上記活性領域
（15b）が上記ゲート絶縁膜（16）と接していることを
特徴とする薄膜トランジスタ。(57) [Claims] Forming a polycrystalline silicon or amorphous silicon semiconductor layer (15) on the insulating substrate (10) on which the source electrode (S) and the drain electrode (D) are formed; The part is melted and activated by light irradiation or local heating to activate the active region (15b), which is an upper layer of the semiconductor layer, and is in contact with the source electrode (S) and the drain electrode (D), which is a lower layer of the semiconductor layer. Manufacturing a thin film transistor, comprising: a step of forming a two-layer structure of a region (15a); and a step of forming a gate electrode (17) on the active region (15b) via a gate insulating film (16). Method. 2. 2. The method according to claim 1, wherein said melting means is an electron beam, a laser, or an infrared heater. 3. 2. The method according to claim 1, wherein the melting is performed after the semiconductor layer (15) is patterned in the melting. 4. 2. The method according to claim 1, wherein the melting is performed after depositing the gate insulating film (16). 5. An insulating substrate (10), a source electrode (S) and a drain electrode (D) formed on the insulating substrate (10), and a semiconductor layer provided in contact with the source electrode (S) and the drain electrode (D). 15) and a gate insulating film (1) on the semiconductor layer (15)
And a gate electrode (D) formed therethrough. The semiconductor layer (15) has a two-layer structure of a lower inactive region (15a) and an upper melt-solidified active region (15b). And the non-active region (15a) corresponds to the source electrode (S).
And a drain electrode (D), and the active region (15b) is in contact with the gate insulating film (16).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61191691A JP2735177B2 (en) | 1986-08-18 | 1986-08-18 | Thin film transistor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61191691A JP2735177B2 (en) | 1986-08-18 | 1986-08-18 | Thin film transistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6347980A JPS6347980A (en) | 1988-02-29 |
| JP2735177B2 true JP2735177B2 (en) | 1998-04-02 |
Family
ID=16278856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61191691A Expired - Fee Related JP2735177B2 (en) | 1986-08-18 | 1986-08-18 | Thin film transistor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2735177B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2607147B2 (en) * | 1989-06-12 | 1997-05-07 | 松下電子工業株式会社 | Image display device and method of manufacturing the same |
| JP2889924B2 (en) * | 1989-06-30 | 1999-05-10 | 日本電信電話株式会社 | Manufacturing method of thin film field effect transistor |
| EP0465264B1 (en) * | 1990-07-06 | 1998-12-09 | Kazuo Tsubouchi | Metal film forming method |
| EP0473988A1 (en) * | 1990-08-29 | 1992-03-11 | International Business Machines Corporation | Method of fabricating a thin film transistor having amorphous/polycrystalline semiconductor channel region |
| US5471330A (en) * | 1993-07-29 | 1995-11-28 | Honeywell Inc. | Polysilicon pixel electrode |
| TWI224868B (en) | 2003-10-07 | 2004-12-01 | Ind Tech Res Inst | Method of forming poly-silicon thin film transistor |
| WO2011141948A1 (en) * | 2010-05-10 | 2011-11-17 | パナソニック株式会社 | Thin film transistor device and method for manufacturing thin film transistor device |
| US11362215B2 (en) | 2018-03-30 | 2022-06-14 | Intel Corporation | Top-gate doped thin film transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58206121A (en) * | 1982-05-27 | 1983-12-01 | Toshiba Corp | Manufacture of thin-film semiconductor device |
| JPS60109282A (en) * | 1983-11-17 | 1985-06-14 | Seiko Epson Corp | Semiconductor device |
-
1986
- 1986-08-18 JP JP61191691A patent/JP2735177B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6347980A (en) | 1988-02-29 |
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