JPS58196863U - 半導体レ−ザ用サブマウント - Google Patents

半導体レ−ザ用サブマウント

Info

Publication number
JPS58196863U
JPS58196863U JP9554682U JP9554682U JPS58196863U JP S58196863 U JPS58196863 U JP S58196863U JP 9554682 U JP9554682 U JP 9554682U JP 9554682 U JP9554682 U JP 9554682U JP S58196863 U JPS58196863 U JP S58196863U
Authority
JP
Japan
Prior art keywords
semiconductor laser
melting point
submount
gold
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9554682U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6244552Y2 (enExample
Inventor
茨木 晃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9554682U priority Critical patent/JPS58196863U/ja
Publication of JPS58196863U publication Critical patent/JPS58196863U/ja
Application granted granted Critical
Publication of JPS6244552Y2 publication Critical patent/JPS6244552Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
JP9554682U 1982-06-24 1982-06-24 半導体レ−ザ用サブマウント Granted JPS58196863U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9554682U JPS58196863U (ja) 1982-06-24 1982-06-24 半導体レ−ザ用サブマウント

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9554682U JPS58196863U (ja) 1982-06-24 1982-06-24 半導体レ−ザ用サブマウント

Publications (2)

Publication Number Publication Date
JPS58196863U true JPS58196863U (ja) 1983-12-27
JPS6244552Y2 JPS6244552Y2 (enExample) 1987-11-25

Family

ID=30228122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9554682U Granted JPS58196863U (ja) 1982-06-24 1982-06-24 半導体レ−ザ用サブマウント

Country Status (1)

Country Link
JP (1) JPS58196863U (enExample)

Also Published As

Publication number Publication date
JPS6244552Y2 (enExample) 1987-11-25

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