JPS58186839A - 並列加算回路 - Google Patents
並列加算回路Info
- Publication number
- JPS58186839A JPS58186839A JP57068447A JP6844782A JPS58186839A JP S58186839 A JPS58186839 A JP S58186839A JP 57068447 A JP57068447 A JP 57068447A JP 6844782 A JP6844782 A JP 6844782A JP S58186839 A JPS58186839 A JP S58186839A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- parallel
- clock signal
- counter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57068447A JPS58186839A (ja) | 1982-04-23 | 1982-04-23 | 並列加算回路 |
GB08310853A GB2119979A (en) | 1982-04-23 | 1983-04-21 | Frequency divider |
US06/487,422 US4508000A (en) | 1982-04-23 | 1983-04-21 | Frequency-selectable signal generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57068447A JPS58186839A (ja) | 1982-04-23 | 1982-04-23 | 並列加算回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58186839A true JPS58186839A (ja) | 1983-10-31 |
JPH0412488B2 JPH0412488B2 (enrdf_load_stackoverflow) | 1992-03-04 |
Family
ID=13373962
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57068447A Granted JPS58186839A (ja) | 1982-04-23 | 1982-04-23 | 並列加算回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58186839A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0239099A (ja) * | 1988-07-28 | 1990-02-08 | Ricoh Co Ltd | 楽音発生装置 |
-
1982
- 1982-04-23 JP JP57068447A patent/JPS58186839A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0239099A (ja) * | 1988-07-28 | 1990-02-08 | Ricoh Co Ltd | 楽音発生装置 |
Also Published As
Publication number | Publication date |
---|---|
JPH0412488B2 (enrdf_load_stackoverflow) | 1992-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4241408A (en) | High resolution fractional divider | |
US3855459A (en) | Apparatus for converting data into the same units | |
US4727507A (en) | Multiplication circuit using a multiplier and a carry propagating adder | |
US4508000A (en) | Frequency-selectable signal generator | |
JPS58186839A (ja) | 並列加算回路 | |
US5070312A (en) | Pulse width modulation circuit of programmable subframe system | |
US3373269A (en) | Binary to decimal conversion method and apparatus | |
US4763297A (en) | Monolithic integrated digital circuit including an internal clock generator and circuitry for processing multi-digit signals | |
SU1280624A1 (ru) | Устройство дл умножени чисел с плавающей зап той | |
JPS6328368B2 (enrdf_load_stackoverflow) | ||
JPS59190724A (ja) | 周波数可変のパルス発生器 | |
SU1441389A1 (ru) | Устройство дл делени | |
JPS51130266A (en) | Electronic clock | |
SU985783A1 (ru) | Устройство дл умножени п-разр дных чисел | |
SU517152A1 (ru) | Умножитель частоты периодических импульсов | |
JPS55110343A (en) | Arithmetic circuit | |
SU1266009A1 (ru) | Устройство дл формировани интегральных характеристик модул рного кода | |
SU1264168A1 (ru) | Генератор псевдослучайной последовательности | |
JP2708979B2 (ja) | シフト加算方式を用いた乗算回路 | |
SU1658147A1 (ru) | Устройство дл умножени чисел | |
SU864283A1 (ru) | Устройство дл суммировани | |
SU1472899A1 (ru) | Устройство дл умножени | |
SU1403061A1 (ru) | Устройство дл выполнени операций умножени и делени | |
SU1166104A1 (ru) | Устройство дл вычислени синусно-косинусных зависимостей | |
SU468239A1 (ru) | Дес тичное множительное устройство |