JPS5815394A - 通話路メモリの二重化方式 - Google Patents

通話路メモリの二重化方式

Info

Publication number
JPS5815394A
JPS5815394A JP11301281A JP11301281A JPS5815394A JP S5815394 A JPS5815394 A JP S5815394A JP 11301281 A JP11301281 A JP 11301281A JP 11301281 A JP11301281 A JP 11301281A JP S5815394 A JPS5815394 A JP S5815394A
Authority
JP
Japan
Prior art keywords
information
memory
channel memory
communication path
main
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11301281A
Other languages
English (en)
Japanese (ja)
Other versions
JPH045315B2 (enExample
Inventor
Yoshiharu Kamio
神尾　由治
Masato Fujisawa
藤沢　真人
Yoshikazu Tanaka
良和 田中
Shoji Nojiri
野尻　昭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11301281A priority Critical patent/JPS5815394A/ja
Publication of JPS5815394A publication Critical patent/JPS5815394A/ja
Publication of JPH045315B2 publication Critical patent/JPH045315B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP11301281A 1981-07-21 1981-07-21 通話路メモリの二重化方式 Granted JPS5815394A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11301281A JPS5815394A (ja) 1981-07-21 1981-07-21 通話路メモリの二重化方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11301281A JPS5815394A (ja) 1981-07-21 1981-07-21 通話路メモリの二重化方式

Publications (2)

Publication Number Publication Date
JPS5815394A true JPS5815394A (ja) 1983-01-28
JPH045315B2 JPH045315B2 (enExample) 1992-01-31

Family

ID=14601218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11301281A Granted JPS5815394A (ja) 1981-07-21 1981-07-21 通話路メモリの二重化方式

Country Status (1)

Country Link
JP (1) JPS5815394A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6135698A (ja) * 1984-07-27 1986-02-20 Fujitsu Ltd 時分割通話路装置の系選択方式
JPS61169015A (ja) * 1985-01-23 1986-07-30 Hitachi Ltd フリツプフロツプ回路
US5096182A (en) * 1984-10-19 1992-03-17 Canon Kabushiki Kaisha Cut sheet holding and feeding apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5176904A (ja) * 1974-12-27 1976-07-03 Nippon Telegraph & Telephone Tokibunkatsutsuwaroyobihoshiki

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5176904A (ja) * 1974-12-27 1976-07-03 Nippon Telegraph & Telephone Tokibunkatsutsuwaroyobihoshiki

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6135698A (ja) * 1984-07-27 1986-02-20 Fujitsu Ltd 時分割通話路装置の系選択方式
US5096182A (en) * 1984-10-19 1992-03-17 Canon Kabushiki Kaisha Cut sheet holding and feeding apparatus
JPS61169015A (ja) * 1985-01-23 1986-07-30 Hitachi Ltd フリツプフロツプ回路

Also Published As

Publication number Publication date
JPH045315B2 (enExample) 1992-01-31

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