JPS58153349A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58153349A
JPS58153349A JP3616582A JP3616582A JPS58153349A JP S58153349 A JPS58153349 A JP S58153349A JP 3616582 A JP3616582 A JP 3616582A JP 3616582 A JP3616582 A JP 3616582A JP S58153349 A JPS58153349 A JP S58153349A
Authority
JP
Japan
Prior art keywords
silicon dioxide
silicon
groove
sio2
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3616582A
Other languages
Japanese (ja)
Inventor
Toshiyuki Ishijima
石嶋 俊之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3616582A priority Critical patent/JPS58153349A/en
Publication of JPS58153349A publication Critical patent/JPS58153349A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/763Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To isolate elements adapted for a high integration by forming a vertical groove in an Si substrate, covering SiO2 film, superposing polysilicon, etching to the boundary of the SiO2 film, then oxidizing the polysilicon and etching the SiO2 to the surface of the substrate. CONSTITUTION:Two layer mask of SiO2 22' and Si3N4 23' is formed on an n type Si substrate 21, etched by reactively sputtering to form a vertical groove, an SiO2 film 27 is covered, and an n type layer 26 is formed by ion implantation in the bottom of the groove. Polysilicon 27B is superposed by a CVD method through an SiO2 27A, a flat surface is formed, and the layer 27B is etched to the boundary of the layer 27A. The polysilicon 27B' which remain in the groove is converted into an SiO2 27B'', with the Si3N4 film 23' as a mask the films 27A, 27B'' are etched to the surface of the substrate, and when the films 23', 22' are then removed, no bird beak is produced, the surface is flat, and an element adapted for high integration can be isolated.

Description

【発明の詳細な説明】 本a−は亭導体装置O製造方法、411Kその素子間を
分離し喪中導体装置O製造方法に関するものであ為・ 第1−は、従来知られているシリコン基板と窒化珪素膜
上に、熱酸化法により形成される酸化膜の成長速度差を
利用した選択酸化法による素子分離の製造プロセスを示
し丸亀のである。
DETAILED DESCRIPTION OF THE INVENTION This article a- relates to a method for manufacturing a conductor device O, 411K, and a method for manufacturing a conductor device O by separating its elements. A manufacturing process for element isolation using a selective oxidation method that utilizes the growth rate difference of oxide films formed on a silicon nitride film by a thermal oxidation method is shown in Marugame.

第1図(a)はシリコン結晶基板11のII!面に、熱
酸化法によシ二酸化珪素膜12を形成し、次いでその上
に11化珪素1[13を形成し、さらに熱酸化法により
窒化珪素1[1!上に二酸化珪fIAJl[14を形成
した後、素子領域形状を有するホトレジスト15を形成
し九状態を示す。
FIG. 1(a) shows II! of the silicon crystal substrate 11! A silicon dioxide film 12 is formed on the surface by thermal oxidation, then silicon 11ide 1[13 is formed thereon, and silicon nitride 1[1!] is further formed by thermal oxidation. After forming silicon dioxide fIAJl[14 on top, a photoresist 15 having an element region shape is formed to show nine states.

第1色価)はホトレジスト15を耐腐蝕マスクとして、
二酸化珪素膜14を腐蝕除去して素子領域形状を有する
二酸化珪素@14’を形成し後、ホトレジスト15を除
去した状態を示す。
The first color value) uses photoresist 15 as a corrosion-resistant mask,
A state in which the photoresist 15 is removed after the silicon dioxide film 14 is etched away to form silicon dioxide@14' having the shape of an element region is shown.

第1図((1)は二酸化珪素膜14′を耐腐蝕マスクと
し窒化珪素l[15を腐蝕除去し、素子領域形状を有す
る量化珪素膜15′を形成し要領、この窒化珪素1[1
M′を耐拡散マスクとして非素子領域に基板11と同一
導電製の不純物16を拡散し九状態を示す。
FIG. 1 ((1) shows how silicon nitride l[15 is etched away using silicon dioxide film 14' as a corrosion-resistant mask to form a quantized silicon film 15' having an element region shape.
Using M' as a diffusion-resistant mask, an impurity 16 having the same conductivity as that of the substrate 11 is diffused into a non-element region to show nine states.

第1図(イ)社窒化珪素11[1!S’を耐酸化マスク
として熱酸化を行ない、非素子領域に厚い二酸化珪素属
17を形成し良状態を示す。
Figure 1 (a) Silicon nitride 11 [1! Thermal oxidation is performed using S' as an oxidation-resistant mask, and a thick silicon dioxide layer 17 is formed in the non-element region, indicating a good condition.

第1図(・)は二酸化珪素膜14’ 、 @化珪素1墨
1除去して素子分−を行なり良状態を示す。
FIG. 1 (·) shows a good condition after removing the silicon dioxide film 14' and the silicon oxide film 1 and removing the element.

しかしながら、従来のこの選択酸化法にょヤ素子分離を
行なうと自には、非素子領域上に厚い二酸化珪素膜を形
威する際に、いわゆるバーズビークが生じて素子領域幅
を狭めるという欠点がある。
However, the conventional selective oxidation method for device isolation has the disadvantage that when forming a thick silicon dioxide film on a non-device region, a so-called bird's beak occurs and the width of the device region is narrowed.

素子の集積化が進んでいる現在、素子寸法は微細化の一
過をたどっている。このような中で、前述しえような選
択酸化法による素子分離における素子領域幅O狭ば壇ヤ
は大きな問題である。っまシパーズビータ量を初めから
考えてこの二酸化珪素O喰込与分をあらかじめマスク寸
法に見込まねばならず、ζ0ことが大容量集積回路を製
造する場合Kfツブ寸法に大暑な影響を及ぼしていた。
At present, as elements become more integrated, the dimensions of the elements are gradually becoming smaller. Under these circumstances, the narrowness of the device region width O in device isolation by the selective oxidation method described above is a major problem. It is necessary to take into consideration the amount of sipper beater from the beginning and take into account the amount of silicon dioxide O added to the mask dimensions in advance, and ζ0 has a great effect on the Kf profile dimensions when manufacturing large-capacity integrated circuits.

本発明は、非素子領域に素子分離のための熱酸化膜を成
長させる−に生じる素子領域への酸化膜の喰込みいわゆ
るバーズビークを防いで素子領域幅の狭ばま)をなくし
かつ素子表面の平担化を行なうことによp高集積化に適
した素子分離構造の半導体装置の製造方法を提供するも
のである。
The present invention prevents so-called bird's beak, which occurs when a thermal oxide film is grown for device isolation in a non-device region, and eliminates the narrowing of the device region width. The present invention provides a method for manufacturing a semiconductor device having an element isolation structure suitable for high integration by performing planarization.

すなわち、本発明は、半導体基板にエツチングにより溝
を形成した後肢溝にCVD法によシニ参化珪素を形成す
る工程、さらに前記溝を多結晶シリコンで埋めて表面を
平担にする工程、前記多結晶シリコンを前記溝部に残こ
すように前記二酸化珪素膜界面下までエツチング除去す
る工程、前記溝部に残した多結晶シリコンを酸化して半
導体基板表面下まで二酸化珪素を形成し同時に表面を平
担化する工程、半導体基板上に形成した二酸化珪素膜を
半導体基板表面までエツチング除去する工程を行なうこ
とを特徴とするものである。
That is, the present invention includes a step of forming silicon silicate by CVD in a hindlimb groove formed by etching a groove in a semiconductor substrate, a step of filling the groove with polycrystalline silicon to make the surface flat, a step of etching away polycrystalline silicon to below the silicon dioxide film interface so as to leave it in the groove, oxidizing the polycrystalline silicon left in the groove to form silicon dioxide down to the surface of the semiconductor substrate, and at the same time flattening the surface. This method is characterized by performing a step of etching the silicon dioxide film formed on the semiconductor substrate down to the surface of the semiconductor substrate.

以下本発明の典型的な一実施例について第2図を用いて
詳述する。
A typical embodiment of the present invention will be described in detail below with reference to FIG.

第2図(1)は、シリコン結晶基板21上に、熱酸化法
によ)二酸化珪素J[22を形成し、その上に窒化珪素
膜23を形成し、さらに素子領域形状を有するホトレジ
スト25を形成した状態を示す。
In FIG. 2(1), silicon dioxide J[22] is formed on a silicon crystal substrate 21 by a thermal oxidation method, a silicon nitride film 23 is formed thereon, and a photoresist 25 having an element region shape is further formed. Shows the formed state.

第2図(b)は、ホトレジスト25を耐スパツタエツチ
ングマスクとして反応性スパッタエツチングにより下地
の窒化珪素膜21.二酸化珪素膜22およびシリコン結
晶基板21をエツチング除去し、溝Aを形成した後ホト
レジス)25を除去した状態を示す〇第2図(c)は、
前記溝部Aの表面に二酸化珪素膜27を形成し先後、素
子領域を被っている窒化珪素膜2I’を耐イオン注入マ
スクとして溝底部に基板と同−導電一の不純物24をイ
オン注入した状態を示す。
In FIG. 2(b), the underlying silicon nitride film 21 is etched by reactive sputter etching using a photoresist 25 as a sputter etching-resistant mask. Figure 2(c) shows the state in which the silicon dioxide film 22 and the silicon crystal substrate 21 have been etched away, the groove A has been formed, and the photoresist 25 has been removed.
A silicon dioxide film 27 is formed on the surface of the trench A, and an impurity 24 having the same conductivity as the substrate is ion-implanted into the bottom of the trench using the silicon nitride film 2I' covering the element region as an ion implantation-resistant mask. show.

第211(d)は、CVD法K ! D 二酸化珪素1
127jl全面に形威し良状態を示す。このように二酸
化珪素膜27Al形威することKよ°り溝上部の開口部
の形状は逆ハの字となる。このように溝上部の開口部が
逆ハの字蓋となることにより次の工程での溝への多結晶
シリコンoHり込みがよくなり表面を平担にできる。
Section 211(d) is the CVD method K! D silicon dioxide 1
127jl is in good shape throughout. Due to the shape of the silicon dioxide film 27Al, the shape of the opening at the top of the groove becomes an inverted V-shape. Since the opening at the top of the groove forms an inverted V-shaped lid in this manner, polycrystalline silicon OH can be easily penetrated into the groove in the next step, and the surface can be made flat.

第211(@)は、多結晶シリコン273%を全面に成
長させて溝を完全に壌め表面を平担にした状態を示す。
No. 211 (@) shows a state in which 273% polycrystalline silicon is grown over the entire surface, the grooves are completely deepened, and the surface is made flat.

第2[1(f)は、多結晶シリコン17Bを二酸化珪素
膜27Aj9爾下壇でエツチング除去した状態を示す。
The second image 1(f) shows the state in which the polycrystalline silicon 17B is removed by etching below the silicon dioxide film 27Aj9.

第2図(ロ))は、溝部に残した多結晶シリコン27B
′を熱酸化法によシ酸化して二酸化珪素27B#を形成
し、表面を平担化した状態を示す。ただしこの時溝内部
に形成された二酸化後927B’の膜は、シリコン基板
表面下まである程度の深さで達していなければならない
。この量は各製造デバイスによって異なるが 通常のn
チャンネルンリコンゲートMOB)ランジスの場合を例
に取れば4ooOAIi!fの深さで十分である。
Figure 2 (b)) shows the polycrystalline silicon 27B left in the groove.
' is oxidized by a thermal oxidation method to form silicon dioxide 27B#, and the surface is planarized. However, at this time, the 927B' film formed inside the groove after oxidation must reach a certain depth below the surface of the silicon substrate. This amount varies depending on each manufacturing device, but the normal n
Taking the case of Rungis (Channel Recongate MOB) as an example, it is 4ooOAIi! A depth of f is sufficient.

第2図(転)は、表面に形成した二酸化珪素膜27A。FIG. 2 (roll) shows a silicon dioxide film 27A formed on the surface.

27 B’に窒化珪素llI23’を耐エツチングマス
クとしてシリコ、ン基板表面までエツチング除去した後
、窒化珪素膜23′および二酸化珪素膜22′を除去し
て素子分離領域を形成した状態を示す。
27B' shows a state in which the silicon nitride film 23' and the silicon dioxide film 22' are removed to form an element isolation region after etching down to the surface of the silicon substrate using silicon nitride II23' as an etching-resistant mask.

上記工程によって得られた素子領域のせばまりがなくし
かも表面が平担となる0 以上の通シ、本発明によれば、素子分離構造の半導体装
置を製造する際にバーズビークが形晟されず、かつ素子
表面が平担になシさらに溝の深さを深くすることにより
深さ方向に拡がった深い拡散層に対しても同じ分離幅で
素子分離が可能になるほど半導体装置の高集積化に適し
九素子分離を行なうことができる効果を有するものであ
る。
According to the present invention, a bird's beak is not deformed when manufacturing a semiconductor device with an element isolation structure, and the device region obtained by the above process has no constriction and the surface is flat. In addition, the device surface is flat, and by increasing the depth of the groove, it is possible to separate devices with the same separation width even in a deep diffusion layer that spreads in the depth direction, making it suitable for highly integrated semiconductor devices. This has the effect that nine elements can be separated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図−) 、 Cb) 、 (噛) 、 (d) 、
 (・)は、従来知られている選択酸化法を用いること
によって素子間分離を行なう半導体装置O1製造プロセ
スの模式的断面図、第2 ml (a) e (b) 
−(e) 、(d) 、(e) −(f) 、(g) 
−(h)は、本発明〇一実施例をプロセスを追って示し
た模式的断面図である。 21:シリコン基板、22.22’:二酸化珪素膜、2
5.25”、@化珪嵩膜、25:ホトレジスト、26:
チャンネルストツバとしての不純物、27:二酸化珪素
膜、27ム二二酸化珪素膜、27B、27B’:多結晶
シリコン、27r:二酸化珪素膜、A:溝0第2図
Figure 1-), Cb), (bite), (d),
(.) is a schematic cross-sectional view of a semiconductor device O1 manufacturing process that performs element isolation by using a conventionally known selective oxidation method, 2nd ml (a) e (b)
-(e), (d), (e) -(f), (g)
-(h) is a schematic sectional view showing the process of Example 01 of the present invention. 21: Silicon substrate, 22.22': Silicon dioxide film, 2
5.25”, @Silicone film, 25: Photoresist, 26:
Impurity as channel stopper, 27: silicon dioxide film, 27m silicon dioxide film, 27B, 27B': polycrystalline silicon, 27r: silicon dioxide film, A: groove 0 Fig. 2

Claims (1)

【特許請求の範囲】[Claims] (1)  半導体基1[Kエツチングによシ溝を形成し
要領、誼壽KCVD法により二酸化珪素膜を形成する工
程、前記溝を多結晶シリコンで埋めて表面を平担にする
工1、前記多結晶シリコ/を前記溝部に残すように前記
二酸化珪素膜界面下までエツチング除去する工1、前記
溝部に残した多結晶シリコンを酸化して半導体基I[I
IIIilNT壇で二酸化珪素膜を形成し同時に表面を
平担化する1薯、半導体基板上に潜威し九二酸化造素膜
を半導体基板界W首で工y f Vダ瞼査す為工1を行
表うことを4111とする半導体装置OII造方法。
(1) Semiconductor substrate 1 [Procedure of forming grooves by K etching, forming a silicon dioxide film by KCVD method, Step 1 of filling the grooves with polycrystalline silicon to make the surface flat; Step 1 of etching away the polycrystalline silicon to below the interface of the silicon dioxide film so as to leave it in the groove, oxidizing the polycrystalline silicon left in the groove to form a semiconductor substrate I [I
In order to form a silicon dioxide film on the IIIilNT stage and to flatten the surface at the same time, a process 1 was carried out to infiltrate the silicon dioxide film on the semiconductor substrate and inspect the silicon dioxide film on the semiconductor substrate surface. 4111 A method for manufacturing a semiconductor device OII.
JP3616582A 1982-03-08 1982-03-08 Manufacture of semiconductor device Pending JPS58153349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3616582A JPS58153349A (en) 1982-03-08 1982-03-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3616582A JPS58153349A (en) 1982-03-08 1982-03-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS58153349A true JPS58153349A (en) 1983-09-12

Family

ID=12462145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3616582A Pending JPS58153349A (en) 1982-03-08 1982-03-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58153349A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961045A (en) * 1982-09-29 1984-04-07 Fujitsu Ltd Manufacture of semiconductor device
EP0245622A2 (en) * 1986-05-12 1987-11-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
US4766090A (en) * 1986-04-21 1988-08-23 American Telephone And Telegraph Company, At&T Bell Laboratories Methods for fabricating latchup-preventing CMOS device
JPH01120340U (en) * 1988-02-05 1989-08-15
US4983226A (en) * 1985-02-14 1991-01-08 Texas Instruments, Incorporated Defect free trench isolation devices and method of fabrication
US5106777A (en) * 1989-09-27 1992-04-21 Texas Instruments Incorporated Trench isolation process with reduced topography
US5126288A (en) * 1990-02-23 1992-06-30 Rohm Co., Ltd. Fine processing method using oblique metal deposition
WO2006081974A1 (en) * 2005-02-02 2006-08-10 Atmel Germany Gmbh Method for the production of integrated circuits
WO2006081987A1 (en) * 2005-02-02 2006-08-10 Atmel Germany Gmbh Method for producing integrated circuits provided with silicon- germanium hetero-bipolar transistors

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961045A (en) * 1982-09-29 1984-04-07 Fujitsu Ltd Manufacture of semiconductor device
US4983226A (en) * 1985-02-14 1991-01-08 Texas Instruments, Incorporated Defect free trench isolation devices and method of fabrication
US4766090A (en) * 1986-04-21 1988-08-23 American Telephone And Telegraph Company, At&T Bell Laboratories Methods for fabricating latchup-preventing CMOS device
EP0245622A2 (en) * 1986-05-12 1987-11-19 International Business Machines Corporation Trench sidewall isolation by polysilicon oxidation
JPH01120340U (en) * 1988-02-05 1989-08-15
US5106777A (en) * 1989-09-27 1992-04-21 Texas Instruments Incorporated Trench isolation process with reduced topography
US5126288A (en) * 1990-02-23 1992-06-30 Rohm Co., Ltd. Fine processing method using oblique metal deposition
WO2006081974A1 (en) * 2005-02-02 2006-08-10 Atmel Germany Gmbh Method for the production of integrated circuits
WO2006081987A1 (en) * 2005-02-02 2006-08-10 Atmel Germany Gmbh Method for producing integrated circuits provided with silicon- germanium hetero-bipolar transistors
US7459368B2 (en) 2005-02-02 2008-12-02 Atmel Germany Gmbh Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors

Similar Documents

Publication Publication Date Title
JP4796329B2 (en) Manufacturing method of multi-bridge channel type MOS transistor
JP2566380B2 (en) Method for separating semiconductor devices and memory integrated circuit array
US7705417B2 (en) Semiconductor device and method of fabricating isolation region
JPH03155151A (en) Manufacture of semiconductor structure
KR100234408B1 (en) Isolatoin Method for Smiconductor Device
JPS58153349A (en) Manufacture of semiconductor device
JPS58220445A (en) Manufacture of semiconductor integrated circuit
JPS589333A (en) Semiconductor device
JPS5844735A (en) Manufacture of semiconductor device
JPS59177941A (en) Manufacture of element isolation region
JPS60161632A (en) Semiconductor device and manufacture thereof
JPS60136330A (en) Manufacture of complementary metal insulator semiconductor device
JPS60105247A (en) Manufacture of semiconductor device
JPS595645A (en) Manufacture of semiconductor device
JP2690740B2 (en) Method for manufacturing semiconductor integrated circuit device
JPS63142831A (en) Forming method for element separating region of semiconductor device
JPS6079737A (en) Manufacture of semiconductor device
JPS62298157A (en) Manufacture of semiconductor device
JPH01214064A (en) Insulated gate field effect transistor and its manufacture
JPS594046A (en) Semiconductor device and fabrication thereof
JPS6235534A (en) Manufacture of semiconductor device
JPS6352466B2 (en)
JPS63228668A (en) Manufacture of semiconductor device
JPS59208746A (en) Manufacture of semiconductor device
JPH01101649A (en) Element isolation of semiconductor device