JPS63228668A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce soft error by parasitic capacitance and alpha-ray by forming a recessed element forming region through the etching of insulating film, making flat the surface after filling the element forming region with an epitaxial layer and making equal the level difference to thickness of source drain. CONSTITUTION:After forming SiO2 film 2 on a silicon substrate 1, the SiO2 film is etched to form a rectangular recessed element forming region 10 and a groove 3 is provided to expose the surface of silicon substrate 1. Next, Si is grown on the insulating film from the silicon surface of groove and Si is deposited until the stepped portion of SiO2 film 2 is covered. Next, the epitaxial layer 4 of the part which is thicker than the SiO2 is etched for the flattening. Next, a gate oxide film 5 is formed on the surface of epitaxial layer 4, a polycrystalline silicon film including phosphorus of high concentration is deposited and a gate electrode 6 is formed. Thereafter, a source drain region 7 is formed by implanting arsenic. Then, after forming an inter-layer insulating film 8, a contact hole is formed and then an aluminum wiring 9 is formed. Thereby, elements can be isolated easily and soft error by parasitic capacitance and-ray can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

In recent years, in order to increase the density of semiconductor devices, not only the elements themselves have been miniaturized, but also the insulating layer region that separates the elements has been miniaturized, the structure of the element isolation layer has been devised, and silicon has been formed on the insulating film. So I (silicon
Attempts have been made to improve the performance of semiconductor devices using an on-insulator structure.

One of the methods of isolating elements using this SOI structure is
For example, Qi, I, Cummins (T, I.

Kamins) et al.
Electron Device Letters (IEEE ELE
CTRON DEVICE LETTER3)19
In 1984, EDL-5 Vol.
dTransistors in Lateral
CVDEpitaxial 5ilicon-on-I
There is a paper published under the title ``Nsulator Films''.

As shown in FIG. 3, this method involves forming a pattern using the first 5i02 film 22 as an insulating layer on a silicon substrate IA, and selectively epitaxially growing silicon using the silicon substrate at both ends of the pattern as a seed. Then, the epitaxial layer 23 protrudes laterally on the 5i02 pattern, and by further growth, the SiO□ pattern region is completely covered with the epitaxial layer 23 to form an SOI structure.

When semiconductor elements are formed on the 5i02 film, as shown in FIG. 4, the epitaxial silicon layer is subjected to another method for element isolation on the surface, such as trench isolation or selective oxidation isolation, so that each element is separated by a trench. 5i02 membrane 24 inside
They are completely dielectrically isolated by polysilicon 25 etc. buried through them. After that, on the separated epitaxial growth layer, a gate oxide film 5A, a gate electrode 6A, a source and
A semiconductor device such as an MO3 field transistor including the drain region 7A and the like is formed.

[Problem that the invention seeks to solve]

Even if an epitaxial layer is formed on the first SiO2 film as in the conventional manufacturing method described above, there is a problem in that the separation region in the planar direction must be formed by a different method. Furthermore, when forming a semiconductor element on an SOI structure, a thick epitaxial layer as in the conventional example is not necessary; rather, the thickness of the epitaxial layer is determined by the thickness of the source layer.
It is necessary to reduce parasitic capacitance and soft errors due to α rays by making the thickness equal to that of the drain region 7A.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned problems, facilitates element isolation, and reduces soft errors due to parasitic capacitance and alpha rays.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention includes the steps of: forming an insulating film with a concave region in a predetermined portion of a semiconductor substrate to form an element formation region; a step of exposing the surface of the semiconductor substrate by forming a groove in contact with a side; a step of performing epitaxial growth through the exposed surface of the substrate to form an epitaxial layer of a semiconductor thicker than the insulating film in the element formation region; The method includes a step of etching the layer to leave the epitaxial layer only in the concave element forming region and flattening the surface.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip for explaining one embodiment of the present invention, and FIGS. 2(a) to (j) are cross-sectional views shown in order of steps for explaining one embodiment of the present invention. be.

First, FIG. 1 is a sectional view taken along line AA' and line BB' in FIG. As shown in FIGS. 2(a) and (b), a 5i02 film with a thickness of 600 mm was deposited on a silicon substrate 1 by thermal oxidation.
After forming the film 2, the S i 0 in a desired region is etched using lithography technology and reactive ion etching technology.
The two films are etched approximately 1,500 times to form a rectangular concave element forming region 10. Then, using lithography and reactive ion etching again, grooves 3 are formed in desired regions in contact with the long sides of the rectangle, exposing the surface of the silicon substrate 1.

Next, as shown in FIGS. 2(C) and (d), after removing the damaged layer formed on the silicon substrate exposed by reactive ion etching, etching was performed under conditions that would prevent silicon from depositing on the insulating film. Using a certain S i H2Ce2/HCe/Hz mixed gas, Si is selectively grown from the silicon surface of the trench until it covers at least the step part of the 5i02 film 2.
Deposit i.

Next, as shown in FIGS. 2(e) and ('f), the portion of the epitaxial layer 4 that is thicker than the thickness of the 5i02 film 2 is etched by an etch-back method and planarized. For planarization, a selective polishing method is used. may also be used.

Next, as shown in FIGS. 2(g) and 2(h), the surface of the planarized epitaxial layer 4 is thermally oxidized to form a gate oxide film 5 of about 200 layers, followed by a film containing a high concentration of phosphorus. A polycrystalline silicon film is deposited by CVD, and a gate electrode 6 made of polycrystalline silicon is formed at a desired position by lithography and reactive ion etching. Subsequently, arsenic was added at 5X1015cm-2 by ion implantation method.
By implanting and heat-treating the epitaxial layer,
A train region 7 is formed.

Next, as shown in FIGS. 2(i) and (J), a glabellar insulating film 8 made of a 5i02 film is formed by CVD, a contact hole is formed, an At' film is deposited, and then etching is performed. By doing this, an aluminum wiring 9 is formed and a semiconductor element consisting of an n-channel MO3) transistor is completed.

As described above, in this embodiment, the Si○2 film 2 is etched to form a concave element formation region, and an epitaxial layer is deposited in this region to flatten the surface, thereby making it possible to easily isolate the elements. can.

In the above embodiment, the case where an n-channel MOS transistor is formed is explained, but a P-channel MOS transistor is formed.
O3) transistors or complementary MO8) transistors may be formed.

In addition, in the example, the step difference in the SiO2 film in the rectangular element formation region was 1500, but it is not limited to this, and the thickness of the formed source/drain is larger than the step difference in SiO The step may be formed under conditions such that the groove is formed in contact with the short side of the rectangle, but it may be formed on the long side.Also, in the above embodiment, S i 02 is used as the insulating film that defines the element region. I used S.
Other insulating films such as i3N4 may be used. Also, as a method for forming the recesses in the insulating film forming the element isolation region, there is a method such as performing selective oxidation twice. Furthermore, although silicon was selectively epitaxially grown in the above embodiment, Ge and G
It may also be a semiconductor with the same characteristics as a A s.

〔Effect of the invention〕

As explained above, the present invention etches an insulating film to form a concave element formation region, fills this element formation region with an epitaxial layer, and then flattens the surface, thereby easily separating elements. Furthermore, by making the step difference equal to the thickness of the source train, there is an effect that parasitic capacitance and soft errors due to α rays can be reduced. .

[Brief explanation of drawings]

FIG. 1 is a plan view for explaining an embodiment of the present invention, and FIGS. 2(a) to (J) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention, 3 and 4 are cross-sectional views of a semiconductor chip for explaining an example of a conventional method of manufacturing a semiconductor device. 1, IA...silicon substrate, 2...5i02 film, 3
...Groove, 4...Epitaxial layer, 5,5A...
Gate oxide film, 6,6A...gate electrode, 7.7A...
... Source/drain region, 8... Interlayer insulating film, 9.
・・Aff wiring, 22-・first 5i02 film, 24・
-8i02 film, 25... polysilicon, 26... field oxide film. 1wo' 2nd F'U source - F'Ui: / unwritten r 1 s flower 2 mouth A cow 4■

Claims (1)

[Claims] forming an insulating film with a concave region in a predetermined portion on a semiconductor substrate to form an element formation region; and forming a groove in a predetermined portion of the element formation region and in contact with a pair of opposing sides of the semiconductor substrate; a step of exposing the surface, a step of performing epitaxial growth through the exposed substrate surface to form an epitaxial layer of a semiconductor thicker than the insulating film in the element formation region, and etching the epitaxial layer to form the concave element formation region. 1. A method for manufacturing a semiconductor device, comprising: planarizing a surface while leaving an epitaxial layer only inside the semiconductor device.