JPS63228669A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce soft error by providing element forming region by removing a second insulating film formed on a first insulating film, forming a silicon layer within this element forming region and determining level difference of insulating film with thickness of the second insulating film. CONSTITUTION:A silicon oxide film 2 is deposited on a P-type silicon substrate 1 with face orientation 100 and then a silicon nitride film 3 is deposited. Next, the Si3N4 film of the desired region is removed and a rectangular element forming region 20 is formed. Thereafter, a mask 4 having an aperture is formed and an aperture 5 is provided by etching only the SiO2 film 2. Next, a silicon layer 6 which reaches the surface of Si3N4 film 3 is formed by epitaxial growth of Si from the aperture. Next, after etching the silicon layer 6 which is higher than the Si3N4 film 3, a gate oxide film 7 is formed, a polycrystalline silicon film including phosphorus of high concentration is deposited and a gate electrode 8 is formed. Thereafter, arsenic is implanted, an interlayer insulating film 10 is formed after forming a source drain region 9 to the silicon layer 6, and an Al wiring 11 is formed by opening a contact hole. Thereby, elements can be easily isolated and soft error by the parasitic capacitance and alpha-ray can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

In recent years, in order to increase the density and performance of semiconductor devices, attempts have been made to reduce the size of the insulating layer area that separates elements, and to form three-dimensional devices with stacked elements, the structure of the element isolation layer has been improved. So-called SOI (Silicon on Insulation), which forms silicon on an insulating film,
Attempts have been made to improve the performance of semiconductor devices using the lator structure.

One of the methods of isolating elements using this SOI structure is
For example, Qi, I, Cummins (T, I.

IEEE Electron Device Letters (IEEE ELEC) by Kamins et al.
TRONDEVICE LETTERS) 1984, EDL Vol. 5, pp. 449-451.
Transistors in Lateral C
VD Epitaxial 5ilicon-on-I
There is a paper published under the title ``Nsulator Films''.

As shown in FIG. 3, this method involves forming a pattern using the first 5i02 film 22 as an insulating layer on a silicon substrate lA, and selectively epitaxially growing silicon using the silicon substrate at both ends of the pattern as a seed. Then, the epitaxial layer 23 protrudes laterally on the SiO2 pattern, and by further growth, the SiO2 pattern region is completely covered with the epitaxial layer 23, forming an SOI
It forms the structure.

When semiconductor elements are formed on the 5i02 film, as shown in FIG. 4, the epitaxial silicon layer is subjected to another method for element isolation on the surface, such as trench isolation or selective oxidation isolation, so that each element is separated by a trench. 5i02 membrane 24 inside
They are completely dielectrically isolated by polysilicon 25 etc. buried through them. After that, a source/drain region 9A and a gate oxide film 7A are formed on the separated epitaxial growth layer.
, a gate electrode 8A, etc. A semiconductor element such as an MO8 field effect transistor is formed.

[Problem that the invention seeks to solve]

As in the conventional manufacturing method described above, the first 5iozJ
Even if an epitaxial layer is formed on li, at least
Furthermore, there is a problem in that the separation region in the planar direction must be formed using a different method. Furthermore, when forming a semiconductor element on a horizontal SOI layer, it is not necessary to have a thick epitaxial layer as in the conventional example, but rather, by making the thickness of the epitaxial layer equal to the thickness of the source/drain region 9A, parasitic capacitance can be reduced. It is necessary to reduce the amount of radiation caused by alpha rays and soft errors caused by alpha rays.

An object of the present invention is to provide a method for manufacturing a semiconductor device in which element isolation is easy and soft errors due to parasitic capacitance and α rays are reduced.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a first insulating film and a second insulating film on a silicon substrate, and then removing a predetermined portion of the second insulating film to form an element formation region; forming an opening in the second insulating film in the formation region to expose the surface of the silicon substrate; and epitaxially growing silicon selectively from the opening to reach the element formation region on the surface of the second insulating film. The method includes a step of forming a layer.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) to 1(e) are a plan view and a sectional view showing an embodiment of the present invention in the order of manufacturing steps.

First, let's look at Figure 1(a) and the A-A' line and B of Figure 1(a).
As shown in FIGS. 1(b) and 1(c), which are cross-sectional views taken along the -B' line, silicon oxide ( Si0
2) Deposit film 2 to a thickness of approximately 4000 nm, followed by a second
Silicon nitride (Si3r
'14) Deposit film 3 to a thickness of 1500 nm. Then,
A desired region of the Si3N4 film is removed by lithography technology and dry etching technology to form a rectangular element formation region 20.

Next, as shown in FIG. 1(d) and FIGS. 1(e) and (f), which are a cross-sectional view taken along the line C-C" and a cross-sectional view taken along the line D-D' in FIG. Depending on the process, element formation area 2
After forming a mask 4 made of photoresist having a predetermined opening including a part of one opposite side of the 0, the photoresist, the silicon substrate, and the 5L3N4 film 3 are not etched (only the Si02 film 2 is etched). Openings 5 are formed by reactive ion etching under the following conditions.

Next, as shown in FIG. 1(g) and (h), SiH2C
e2/HC1! Using a /H2 mixed gas system, St is selectively grown epitaxially from the opening 5 without SL growing on the insulating film, reaching the surface of the Si3N4 film 3 on the 5i02 film 2 in the element formation region 20. A thick silicon layer 6 is formed.

Next, as shown in FIGS. 1(i) and (j), the silicon layer 6 in a portion higher than the height of the 5t3N4 film 3 is etched and flattened by an etch-back method, and then the surface of the silicon layer is thermally oxidized. Then, a polycrystalline silicon film containing a high concentration of phosphorus is formed using the CVD method.
The gate electrode 8 is deposited to a thickness of 500 nm and placed at the desired position using lithography and reactive ion etching techniques.
form. Next, arsenic was added at 5× by ion implantation method.
10 "C11-" is implanted to form a region containing highly concentrated arsenic in the silicon layer 6 not covered with the gate electrode, and heat treatment is performed to form the source/drain region 9.

Next, as shown in FIG. 1 uc>, <e>, a glabellar insulating film 10 made of SiO□ is formed by the CVD method, and a contact hole is opened. By depositing a film and patterning it to form an Ae wiring 11, an n-channel MO3
) Complete a semiconductor device consisting of a transistor.

In this way, in this example, the Si on the 5i02 film 2 is
The 3N4 film 3 is etched away to form a concave element formation region 20.
By forming a silicon layer, depositing a silicon layer therein, and planarizing the silicon layer, element isolation can be easily performed. In addition, photoresist and Si are used as a mask for forming the opening 5.
By using the 3N4 film, a rectangular pattern with no rounded corners can be obtained.

Incidentally, in the above embodiment, a case was explained in which a SiO□ film was used as the first insulating film and a Si3N4 film was used as the second insulating film, but the invention is not limited to this, and vice versa, or other methods may be used. A combination using an insulating material may also be used. Further, the thickness of the insulating film is not limited to the value in the example.

Further, although a P-type substrate is used, a P-channel MOS transistor, a CMOS device, etc. may be formed using an n-type substrate.

〔Effect of the invention〕

As described above, according to the present invention, the second insulating film formed on the first insulating film is removed to provide an element formation region, and a silicon layer is formed in this element formation region, thereby facilitating element isolation. Furthermore, since the thickness of the second insulating film determines the level difference in the insulating film, the thickness of the silicon layer is well controlled to be equal to the thickness of the source/drain region, reducing parasitic capacitance and soft errors caused by alpha rays. It has the effect of

[Brief explanation of drawings]

1(a) to 1(e) are a plan view and a cross-sectional view of a semiconductor chip shown in the order of manufacturing steps to explain an embodiment of the present invention, and FIGS. 2 and 3 are conventional manufacturing steps of a semiconductor device. FIG. 3 is a cross-sectional view for explaining the method. 1, IA...silicon substrate, 2...5i02 film, 3
...Si3N4 film, 4...mask, 5...opening, 6...silicon layer, 7.7A...gate oxide film,
8, 8A... Gate electrode, 9, 9A... Source/drain region, 10... Interlayer insulating film, 11... AN wiring, 20... Element formation region, 22... First 5i0
2 film, 23... epitaxial layer, 24...5i0
2 film, 25... polysilicon, 26... field oxide film. ). Ei 1tsu system hand order ■Kiku area゛gyu 1■ 23 Evita^1shiX)L layer 弗3 figure

Claims (1)

[Claims] a step of sequentially forming a first insulating film and a second insulating film on a silicon substrate, and then removing a predetermined portion of the second insulating film to form an element formation region; and forming an opening in the second insulating film in the element formation region. the step of exposing the surface of the silicon substrate by exposing the surface of the silicon substrate; and the step of epitaxially growing silicon selectively from the opening to form a silicon layer in the element formation region reaching up to the surface of the second insulating film. A method for manufacturing a semiconductor device, characterized by: