JPS62298157A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the effects of crystal defects, contamination and the like of a semiconductor substrate yielded by etching, by forming a capacitor insulating film on the surface of a semiconductor film, which is newly formed on the sidewall of a groove that is formed by etching the semiconductor substrate. CONSTITUTION:A first SiO2 film 2, which is formed as a mask for selective etching, is made to remain. A same conductivity type electric isolating impurity layer 4 is formed at the bottom surface of a groove 3, which is formed by etching. A second CVD SiO2 insulating film 5 is formed on the bottom surface of the groove. Only a P-type Si semiconductor substrate 1, which forms the sidewall of the groove, is exposed. A first Si semiconductor film 6 including opposite conductivity type impurites is selectively formed only on the sidewall of the groove. Then, a SiO2 capacitor insulating film 7 is formed on the surface of the first semiconductor film. A second polycrystalline Si semiconductor film 8 including impurities is formed, and the groove is buried. A groove capacitor comprising the first and second semiconductor films 6 and 8 and the capacitor insulating film 7 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Field of Industrial Application The invention relates to semiconductor devices, particularly dynamic memory devices.

Among conventional technology semiconductor devices, dynamic memory (DRAM)
is one of the things that requires the most miniaturization in order to increase its capacitance, and for this reason, trench capacitors that store charge on the side walls of narrow and deep trenches have been proposed, and their structures and manufacturing methods have been proposed and attempted. There is.

Among these methods, the method of using the sidewalls of isolation trenches as capacitors for electrically isolating between elements has a large capacity D because a large amount of accumulated charge can be obtained with a small memory cell area.
This is an effective way to implement RAM.

A conventional technique for forming a capacitor on the sidewall of an isolation trench will be described below.

In FIG. 2, 3 is a groove formed in the S1 substrate, 10.degree. 4 is an n-type impurity layer and a p-type impurity layer, respectively, and 7 is an Si film, an O film, and the like.

The 5i02 film 2 is etched by reactive ion etching (RIE) using a full photoresist mask formed by photolithography on a p-type S1 substrate 1 with an 8102 film 2 formed on its surface, and then Si is etched using the 5102 film 2 as a mask. Grooves 3 are formed by etching the substrate 1 b0 After appropriate cleaning, an n-type impurity is added to the substrate 81 forming the inner wall of the bay 3 to form an n-type impurity layer 1o (FIG. 2a).

Since it is desirable that the n-type impurity layer 1o be thin, S having a small diffusion coefficient in S is often selected as the n-type impurity.
A method in which a film (As glass film) is formed on the inner wall of the groove 3 and thermally diffused into the Si substrate 1 by heat treatment. A method of thermally diffusing ASt into the groove 3 or a method of irradiating the side wall of the groove 3 with accelerated ions in an oblique direction is used.

Next, B is added into Si, which forms the bottom of the groove 3, and the substrate 1.
A type impurity layer 4 is formed to electrically isolate the n-type impurity layers 10 formed on opposite sides of the trench 3 (see FIG. 2b).
). The method of adding B is to prevent it from being injected into the side surface of groove 3.
1 A p-type impurity layer 4 is formed on the bottom surface of the groove by implanting B ions accelerated in a direction perpendicular to the surface of the substrate 1 in an amount sufficiently larger than the n-type impurity of the n-type impurity layer 10 already formed on the bottom surface. .

Subsequently, a thin 5i02 film 7, which will become a capacitor insulating film, is formed on the inner wall of the trench 3 by thermal oxidation (FIG. 2C).

By forming a polycrystalline S1 film 8 doped with P, which is an n-type impurity, and using an etch-back method, polycrystalline S1 is formed in the groove 3.
A capacitor is formed on the side wall of the isolation trench by burying the 5102 film 9 formed by the CVD method after removing the polycrystalline Si film 8 on the upper part of the trench 3 (FIG. 2d).

Problems to be Solved by the Invention In the trench capacitor formed by the above-mentioned conventional technique, since the capacitor insulating film is formed on the surface of the substrate 81 forming the side wall of the trench 3, crystal defects occur during etching. Otherwise, a problem arises in that it is difficult to obtain an insulating film of sufficient quality as a capacitor insulating film due to the influence of contamination and the like.

To solve this problem, a method has been proposed in which after etching, the Si substrate forming the sidewall of the groove 3 is further etched using a method that does not cause crystal defects or contamination, thereby removing the surface layer where crystal defects and contamination exist. However, there is a risk that the shape of the groove 3 once formed may change, and if the width of the groove 3 is narrow and deep, it is difficult to carry out the desired additional etching.

Furthermore, when B ion implantation is used to form the p-type impurity layer 4, which has a higher impurity concentration than the n-type impurity layer 10 already formed on the bottom surface of the trench 3, the sidewall of the trench 3 where the capacitor will be formed is If B ions are also implanted, a part of the n-type impurity layer 10 is converted into a p-type impurity layer, causing a problem that a desired capacitor area cannot be obtained. This problem occurs particularly when the side surfaces of the groove 3 are not vertical but are inclined, and this causes the capacitor area, that is, the amount of accumulated charge, to be largely dependent on the shape of the groove.

Means to Solve the Problem In the present invention, after leaving the first insulating film formed as a selective etching mask and forming an electrically isolating impurity layer of the same conductivity type on the bottom of the groove formed by etching, further etching is performed. A second insulating film is formed on the bottom surface of the trench, and only the semiconductor substrate forming the trench sidewalls is exposed to light, and a first semiconductor film containing impurities of the opposite conductivity type is selectively formed only on the trench sidewalls. Subsequently, a capacitor insulating film is formed on the surface of the first semiconductor film, and a second semiconductor film containing impurities is further formed to substantially fill the trench. A trench capacitor made of a second semiconductor film and a capacitor insulating film is formed.

According to the present invention, the capacitor insulating film is formed on the surface of the semiconductor film newly formed on the trench sidewall, so that a high quality insulating film can be obtained.

Furthermore, since the impurity layer of the same conductivity type for electrical isolation at the bottom of the trench has already been formed before the semiconductor film on the trench sidewall, which will become one electrode of the capacitor, is formed, when forming this impurity layer, even if the trench sidewall is not vertical but is inclined, and even if some of the accelerated ions are implanted into the sidewall, there is no effect on the impurity concentration of the semiconductor film selectively formed thereon.

Furthermore, a second insulating film is formed on the bottom surface of the trench, and the semiconductor films on the opposing trench sidewalls are completely electrically isolated.

Example An embodiment of the present invention will be described with reference to FIG.

In FIG. 1, 1 is a p-type Si substrate, 3 is a groove formed by etching, and 6 is a C V D 5 formed on the bottom of the groove.
The i02 film, 6 is the S1 film selectively formed on the side wall of the groove, and the 5i02 film is shown.

The 5i02 film 2 formed on the surface of the p-type Si substrate 1, which serves as a mask during etching, is etched using a photoresist formed by photolithography as a mask, and then the 5102 film 2 is etched.
Using a mask, the Si substrate 1 is subjected to reactive ion etching (
Etched using RIM) method, width 0.8μm, depth 4μm
A groove 3 of m is formed.

Injecting accelerated B ions in a direction perpendicular to the Si substrate 1,
A p-type impurity layer 4 is formed in the SL substrate 1 forming the bottom surface of the groove 3.

Next, a CV with a thickness of 0.2 μm was formed on the surface of the Si substrate 1 using the CVN method.
D After forming a 5i02 film and applying photoresist to fill the trench 3, etching the photoresist f from the top surface and leaving this photoresist k only at the bottom of the trench 3, then using an isodirectional etching method to perform CVD5 etching. By etching the film, a c V D 5io is formed on the bottom of the groove 3.
2 films 5 are formed (FIG. 1a).

Next, an S1 film 6 containing As as an n-type impurity and having a thickness of 0.15 μm is selectively formed only on the side walls of the groove 3 (FIG. 1b).

This includes SiH4, which is a raw material gas, and A, which is an impurity gas.
When HGI is added to SH3 and a selective epitaxial method is used at 1050'C, the S1 film 6 is not formed on the insulating film but is formed only on the trench sidewall where the substrate 81 is exposed.

Therefore, the Si films 6 formed on the opposing sidewalls of the trench are electrically isolated by the G V D 5iOz film 5 on the bottom of the trench, so that a separation step is not required after the S1 film 6 is formed.

An n-type Si thin film 6 is formed.

A 5102 film 7 having a thickness of 10 nm is formed as a capacitor insulating film on the surface of the Si thin film 6 by thermal oxidation in diluted 02 gas (FIG. 1C).

Thereafter, a polycrystalline Si film containing P as an n-type impurity is formed by the CVN method in the same manner as in the conventional technique, and a polycrystalline Si film 8 is embedded in the groove 3 by an etch-back method. Further groove 3
The inner polycrystalline Si film 8 is removed by O, S μm from above,
A capacitor can be formed on the side surface of the isolation trench by forming a 5102 film with a thickness of 0.5 μm using the cvn method and embedding the 5i02 film 9 in the upper part of the trench 3 using the etch pack method.

In the manufacturing method of the present invention, the step of forming an insulating film on the bottom surface of the groove 3 is one important step, and in addition to the above-mentioned method,
It is also possible to select a method in which an insulating film is formed by a directional film formation method such as an IR deposition method, and then the insulating film on the side surfaces of the trench is removed by isotropic etching. This method takes advantage of the fact that an insulating film with a high etching rate is formed on the side surfaces of the trench, and it is a method with good controllability since there is no need to use photoresist or the like as a mask during etching.

Effects of the Invention As described above, since the capacitor insulating film of the present invention is formed on the surface of a newly formed semiconductor film on the sidewall of a groove formed by etching a semiconductor substrate, it is free from crystal defects and contamination of the semiconductor substrate caused by etching. It is possible to obtain an insulating film with good electrical characteristics without being affected by such factors.

Furthermore, when using an ion implantation method with good controllability and directionality to form a p-type impurity layer on the bottom of the trench for the purpose of electrical isolation, even if B ions are implanted into the semiconductor substrate forming the sidewalls of the trench, Since the CV DSi02 film is formed on the p-type impurity layer doped with B at a high concentration, there is no effect of this B on the S1 film 6 formed thereon.

Another effect is that the S1 film 6 containing n-type impurities can be formed without being affected by the B of the p-type impurity layer, and a capacitor electrode with a desired thickness and impurity concentration can be formed. Moreover, since the impurity is added to the S1 film 6 at the same time as the film is formed, it is possible to omit adding the impurity into the narrow and deep trench.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a part of a capacitor on the side wall of an isolation trench according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a part of the same capacitor according to the prior art. 3... Groove, 4... P-type impurity layer, 5...
...CVD5i02 film, 6...S1 film,
Completed...5i02 film, 8...Polycrystalline S1
film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] A semiconductor substrate of one conductivity type having a first insulating film on the surface of the semiconductor substrate and a groove formed by a selective etching method in a predetermined region is prepared, and an impurity of the same conductivity type is added to the semiconductor substrate forming at least the bottom surface of the groove. a step of forming a second insulating film only on the bottom surface of the trench, a step of forming a first semiconductor film containing an impurity of an opposite conductivity type only on the side surfaces of the trench, and a step of adding a second insulating film to the surface of the semiconductor film. 3. A method for manufacturing a semiconductor device, comprising the steps of forming an insulating film in step 3, and forming a second semiconductor film containing impurities of an opposite conductivity type on the surface of the third insulating film.