JPS58142941U - IC package - Google Patents

IC package

Info

Publication number
JPS58142941U
JPS58142941U JP3914882U JP3914882U JPS58142941U JP S58142941 U JPS58142941 U JP S58142941U JP 3914882 U JP3914882 U JP 3914882U JP 3914882 U JP3914882 U JP 3914882U JP S58142941 U JPS58142941 U JP S58142941U
Authority
JP
Japan
Prior art keywords
package
conductive surface
conductive
multilayer
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3914882U
Other languages
Japanese (ja)
Other versions
JPS6348128Y2 (en
Inventor
徳山　三郎
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP3914882U priority Critical patent/JPS58142941U/en
Publication of JPS58142941U publication Critical patent/JPS58142941U/en
Application granted granted Critical
Publication of JPS6348128Y2 publication Critical patent/JPS6348128Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は従来の平面図と側面図、第３図お
よび第４図は本考案にかかる一実施例の横断面図および
側断面図、第５図は他の実施例の横断面図である。図中
、１はピン、２はＩＣチップ、３は導電メタライズ線、
４はボンデイングパ　。 ラド、１１，１２．１３は本考案になる導電面を示す。1 and 2 are a conventional plan view and a side view, FIGS. 3 and 4 are a cross-sectional view and a side sectional view of one embodiment of the present invention, and FIG. 5 is a cross-sectional view of another embodiment. It is a front view. In the figure, 1 is a pin, 2 is an IC chip, 3 is a conductive metallized line,
4 is bonding pa. Rad, 11, 12, and 13 indicate conductive surfaces according to the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多層セラミックからなるパッケージにおいて、電源用配
線は多層導電層のうち、１層の全面、又は半面、又はそ
れらの面の５０％以上の面積を導電面とし、該導電面か
ら最址距離によってポンディングパッドおよび外部ピン
に接続された構造を、有することを特徴とするＩＣパッ
ケージ。In a package made of multilayer ceramic, the power supply wiring has a conductive surface on the entire surface or half of one of the multilayer conductive layers, or an area of 50% or more of these surfaces, and is bonded according to the maximum distance from the conductive surface. An IC package comprising a structure connected to a pad and an external pin.
JP3914882U 1982-03-18 1982-03-18 IC package Granted JPS58142941U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3914882U JPS58142941U (en) 1982-03-18 1982-03-18 IC package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3914882U JPS58142941U (en) 1982-03-18 1982-03-18 IC package

Publications (2)

Publication Number Publication Date
JPS58142941U true JPS58142941U (en) 1983-09-27
JPS6348128Y2 JPS6348128Y2 (en) 1988-12-12

Family

ID=30050451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3914882U Granted JPS58142941U (en) 1982-03-18 1982-03-18 IC package

Country Status (1)

Country Link
JP (1) JPS58142941U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014207488A (en) * 2004-03-26 2014-10-30 エスシーエー アイピーエルエー ホールディングス インコーポレイテッド Multi-chip module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492789A (en) * 1972-04-28 1974-01-11
JPS495391A (en) * 1972-05-02 1974-01-18

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492789A (en) * 1972-04-28 1974-01-11
JPS495391A (en) * 1972-05-02 1974-01-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014207488A (en) * 2004-03-26 2014-10-30 エスシーエー アイピーエルエー ホールディングス インコーポレイテッド Multi-chip module

Also Published As

Publication number Publication date
JPS6348128Y2 (en) 1988-12-12

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