JPS6348128Y2 - - Google Patents
Info
- Publication number
- JPS6348128Y2 JPS6348128Y2 JP1982039148U JP3914882U JPS6348128Y2 JP S6348128 Y2 JPS6348128 Y2 JP S6348128Y2 JP 1982039148 U JP1982039148 U JP 1982039148U JP 3914882 U JP3914882 U JP 3914882U JP S6348128 Y2 JPS6348128 Y2 JP S6348128Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- conductive surface
- multilayer ceramic
- package
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000919 ceramic Substances 0.000 claims description 12
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Description
【考案の詳細な説明】
(a) 考案の技術分野
本考案はIC（集積回路）パツケージの改良に関
する。[Detailed description of the invention] (a) Technical field of the invention The invention relates to improvements in IC (integrated circuit) packages.
(b) 従来技術と問題点
IC素子がLSI、VLSIと高度に集積化され、こ
れを収納するICパツケージも大型となりまたピ
ン数（外部ピン数）も増大してきた。このように
高集積化されると、その信頼度は益重要で、パツ
ケージも絶縁性、耐湿性などにすぐれたセラミツ
クパツケージが重用されている。例えばランダム
ロジツク回路を構成するLSIはピン数も48本ある
いは64本と非常に多い多層セラミツクパツケージ
を使用している。(b) Conventional technology and problems IC elements have become highly integrated into LSI and VLSI, and the IC packages that house them have also become larger and the number of pins (external pins) has also increased. With such high integration, reliability is important, and ceramic packages, which have excellent insulation and moisture resistance, are increasingly used. For example, LSIs that make up random logic circuits use multilayer ceramic packages with a large number of pins, 48 or 64.
第１図はかような多層セラミツクパツケージの
一例として40本のピン数をもつた多層セラミツク
パツケージの平面図を示し、第２図はその側面図
である。このような多ピン構造のICパツケージ
において、VccやGND（接地）のような電源ライ
ンは、最外側端のピンに入力する構成が採られて
おり、これはICを実装する回路基板からの要求
により定められる。例えば、第１図で、ピン１の
No.20をGNDとし、No.40をVccとした形式が多い。
しかし、この最外側端のピン位置から中心位置に
取り付けたICチツプ２まではパツケージ内部の
導電メタライズ線３が最も長く、したがつて、こ
の導電線は高インピータンスとなつて、それより
発生するノイズが、入力レベル特性や耐ノイズ特
性のような素子特性を劣化させる欠点がある。 FIG. 1 shows a plan view of a multilayer ceramic package having 40 pins as an example of such a multilayer ceramic package, and FIG. 2 is a side view thereof. In such multi-pin IC packages, power lines such as Vcc and GND (ground) are input to the outermost pins, which is required by the circuit board on which the IC is mounted. Defined by. For example, in Figure 1, pin 1
There are many formats where No. 20 is set to GND and No. 40 is set to Vcc.
However, the conductive metallized wire 3 inside the package is the longest from the pin position at the outermost end to the IC chip 2 attached at the center position, and therefore this conductive wire has a high impedance. There is a drawback that noise deteriorates device characteristics such as input level characteristics and noise resistance characteristics.
(c) 考案の目的
本考案はこのような特性の劣化を解消させて、
ICの素子特性を向上させるICパツケージを提案
するものである。(c) Purpose of the invention This invention eliminates this deterioration of characteristics,
This paper proposes an IC package that improves IC element characteristics.
(d) 考案の構成
その目的は、多層セラミツク構造のICパツケ
ージにおいて、
該多層セラミツク内部に設ける、多層導電層の
うちの１層の半面を電源用導電面、他の半面を接
地用導電面とし、ボンデイングパツド及び外部接
続用のピンを該導電面に最短距離で接続する構造
とし、且つ該導電面に部分的な欠落部を設けたこ
とを特徴とするICパツケージにより、達成され
る。(d) Structure of the device The purpose is to create an IC package with a multilayer ceramic structure in which one half of one of the multilayer conductive layers provided inside the multilayer ceramic is used as a conductive surface for power supply and the other half as a conductive surface for grounding. This is achieved by an IC package having a structure in which bonding pads and external connection pins are connected to the conductive surface at the shortest distance, and the conductive surface is provided with a partial cutout.
(e) 考案の実施例
図面を参照して、実施例によつて説明すると、
第３図は多層導電層のうち、１層の半面づつを電
源用配線とした一実施例の横断面図を示しており
従来の多層導電層に更に１層を加えて、図示のよ
うな半面を導電メタライズ面とし、左半面１１を
Vcc用として、No.40ピンに最短位置で接続し右半
面１２をGND用としてNo.２０ピンに最短位置で
接続している。これらのメタライズ面に欠落部Ｓ
が設けてあり、この欠落部Ｓの合計面積は、導電
層の上下の多層セラミツクの接着強度を保持する
ため、導電層の総面積の50％以下にする。次の第
４図はその側断面図を示し、ボンデイングパツド
４と、これらの導電面１１，１２とがセラミツク
基板内のスルーホールを通して最短距離で接続さ
れる状態を図示したものである。また、第４図で
スルーホールに代りダイステージの側面Ｄに上下
導電層を設けてもよい。(e) Examples of the invention Referring to the drawings, the invention will be explained by examples.
Figure 3 shows a cross-sectional view of an embodiment in which one half of each layer of the multilayer conductive layer is used as wiring for power supply. is the conductive metallized surface, and the left half surface 11 is
For Vcc, it is connected to the No. 40 pin at the shortest position, and the right half 12 is connected to the No. 20 pin for GND at the shortest position. There are missing parts S on these metallized surfaces.
The total area of the missing portions S is set to be 50% or less of the total area of the conductive layer in order to maintain the adhesive strength of the multilayer ceramics above and below the conductive layer. The following FIG. 4 shows a side sectional view of the bonding pad 4 and the conductive surfaces 11, 12 connected to each other by the shortest distance through a through hole in the ceramic substrate. Further, in place of the through holes in FIG. 4, upper and lower conductive layers may be provided on the side surface D of the die stage.
また電源Vccは２系統を使用する場合もあり、
収納するICチツプの回路を考慮して、全面ある
いは半面を使い分けて構成することが好ましい。 In addition, two power supply Vcc systems may be used.
It is preferable to configure the structure by using either the entire surface or a half surface in consideration of the circuit of the IC chip to be accommodated.
(f) 考案の効果
以上の実施例から判るように、本考案は多層セ
ラミツク内に設けた多層導電層の内の１層を、電
源ラインのVcc，GNDの導電路として用い、そ
のインピーダンスを低下させ、対ノイズ特性など
の電気的特性を向上させるもので、ICの素子特
性の改善に著しい効果のあるものであり、且つ導
電層の部分的な欠落部を導電層の総面積の50％以
下にするので、多層セラミツクの接着強度を保持
することが可能である。そして本考案によれば電
源用、接地用のための導電メタライズ面が１層で
済むため、電気特性の改善された、しかも小型の
ICパツケージを実現できる利点があります。(f) Effect of the invention As can be seen from the above examples, the invention uses one of the multilayer conductive layers provided in the multilayer ceramic as a conductive path for the Vcc and GND of the power supply line, reducing its impedance. It improves the electrical characteristics such as anti-noise characteristics, and has a remarkable effect on improving the device characteristics of IC.It also reduces the partial missing parts of the conductive layer to 50% or less of the total area of the conductive layer. Therefore, it is possible to maintain the adhesive strength of multilayer ceramic. According to the present invention, only one layer of conductive metallization is required for power supply and grounding, resulting in improved electrical characteristics and a compact design.
It has the advantage of being able to realize IC packaging.
第１図および第２図は従来の平面図と側面図、
第３図および第４図は本考案にかかる一実施例の
横断面図および側断面図。
図中、１はピン、２はICチツプ、３は導電メ
タライズ線、４はボンデングパツド、１１，１
２、は本考案になる導電層、Ｓは欠落部を示す。
Figures 1 and 2 are a conventional plan view and side view,
3 and 4 are a cross-sectional view and a side sectional view of one embodiment of the present invention. In the figure, 1 is a pin, 2 is an IC chip, 3 is a conductive metallized line, 4 is a bonding pad, 11, 1
2 indicates a conductive layer according to the present invention, and S indicates a missing portion.
Claims (1)
の１層の半面を電源用導電面、他の半面を接地用
導電面とし、ボンデイングパツド及び外部接続用
のピンを該導電面に最短距離で接続する構造と
し、且つ該導電面に、部分的な欠落部を設けたこ
とを特徴とするICパツケージ。[Claims for Utility Model Registration] An IC package with a multilayer ceramic structure, in which one half of the multilayer conductive layers provided inside the multilayer ceramic is a conductive surface for power supply, and the other half is a conductive surface for grounding, An IC package characterized by having a structure in which a bonding pad and an external connection pin are connected to the conductive surface at the shortest distance, and the conductive surface is provided with a partial cutout.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3914882U JPS58142941U (en) | 1982-03-18 | 1982-03-18 | IC package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3914882U JPS58142941U (en) | 1982-03-18 | 1982-03-18 | IC package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58142941U JPS58142941U (en) | 1983-09-27 |
| JPS6348128Y2 true JPS6348128Y2 (en) | 1988-12-12 |
Family
ID=30050451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3914882U Granted JPS58142941U (en) | 1982-03-18 | 1982-03-18 | IC package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58142941U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224942A1 (en) * | 2004-03-26 | 2005-10-13 | Fan Ho | Semiconductor device with a plurality of ground planes |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492789A (en) * | 1972-04-28 | 1974-01-11 | ||
| JPS495391A (en) * | 1972-05-02 | 1974-01-18 |
-
1982
- 1982-03-18 JP JP3914882U patent/JPS58142941U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492789A (en) * | 1972-04-28 | 1974-01-11 | ||
| JPS495391A (en) * | 1972-05-02 | 1974-01-18 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58142941U (en) | 1983-09-27 |
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