JP4813786B2 - Integrated circuit and integrated circuit assembly - Google Patents

Integrated circuit and integrated circuit assembly Download PDF

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JP4813786B2
JP4813786B2 JP2004283743A JP2004283743A JP4813786B2 JP 4813786 B2 JP4813786 B2 JP 4813786B2 JP 2004283743 A JP2004283743 A JP 2004283743A JP 2004283743 A JP2004283743 A JP 2004283743A JP 4813786 B2 JP4813786 B2 JP 4813786B2
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substrate
integrated circuit
semiconductor substrate
interconnect
bonding pads
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JP2005117038A (en
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マイケル・ジー・ケリー
ラヴィンダー・ケー・コー
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アバゴ・テクノロジーズ・ジェネラル・アイピー（シンガポール）プライベート・リミテッド
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Description

集積回路技術、より具体的には、集積回路パッケージング技術は従来から周知である。フリップチップボンディングと呼ばれるパッケージング技術の１つは、特にＩ／Ｏ数が比較的に多いデバイスに好適である。フリップチップボンディングの場合、集積回路はそのメタライゼーション上に設けられた半田／バンプによりパッケージ基板へと直接的にボンディングされる。一般に多層であるパッケージ基板は、基板中のバイアを通じて半田／バンプと選択的に接触する導電性パターンの層を備えている。フリップチップボンディングは配電インピーダンス(power supply distribution)が低く、その結果、電源電圧ノイズが低くなることから望ましいものである。しかしながら、フリップチップボンディングは高コストとなる場合がある。コストが高くなってしまうのは、主にパッケージ基板に要求される非常に高い実装効率(routing density)によるものである。   Integrated circuit technology, more specifically integrated circuit packaging technology, is well known in the art. One packaging technique called flip chip bonding is particularly suitable for devices with a relatively large number of I / Os. In the case of flip chip bonding, the integrated circuit is bonded directly to the package substrate by solder / bumps provided on the metallization. A package substrate, which is typically multilayer, includes a layer of conductive pattern that selectively contacts solder / bumps through vias in the substrate. Flip chip bonding is desirable because of its low power supply distribution and, as a result, low power supply voltage noise. However, flip chip bonding can be expensive. The increase in cost is mainly due to the very high routing density required for the package substrate.

ワイヤボンディングは、もう１つの周知のパッケージング技術である。この技術では、集積回路は複数のボンディングパッドを備えている。パッケージ基板もボンディングパッドを備えている。集積回路のボンディングパッドは、パッケージ基板のボンディングパッドとワイヤボンディングされている。ワイヤボンディングは一般に低コスト技術である。この技術においては、パッケージ基板の実装効率に対する要求は大幅に低い。   Wire bonding is another well-known packaging technique. In this technique, the integrated circuit includes a plurality of bonding pads. The package substrate also has bonding pads. The bonding pads of the integrated circuit are wire bonded to the bonding pads of the package substrate. Wire bonding is generally a low cost technology. In this technology, the requirement for the mounting efficiency of the package substrate is significantly low.

低コストのアプリケーションの中にはワイヤボンディングによれば実現可能であるが、経済的な理由からフリップチップボンディングをボンディング技術として採用することが難しいものは多数ある。しかしながら、フリップチップボンディングを使用すれば、集積回路全体にわたる配電という意味においてこれらのアプリケーションの多くはその利点の恩恵を受けることができるものである。本発明はこの問題を、フリップチップボンディングおよびワイヤボンディングの両方の利点を併せ持つ低コスト集積回路により解決しようというものである。   Some low-cost applications can be realized by wire bonding, but for economic reasons it is difficult to adopt flip chip bonding as a bonding technique. However, using flip chip bonding, many of these applications can benefit from the benefits in terms of power distribution throughout the integrated circuit. The present invention seeks to solve this problem with a low cost integrated circuit that combines the advantages of both flip chip bonding and wire bonding.

本発明の一態様によれば、本発明は、第一の複数のボンディングパッドを備えた集積回路パッケージと、集積回路パッケージ中にあり、第二の複数のボンディングパッドを備え、ある表面積を有する半導体基板と、そして第一の複数のボンディングパッドの選択されたものと第二の複数のボンディングパッドの選択されたものを接続する複数のワイヤボンドを備えた集積回路を提供するものである。半導体基板上には相互接続基板が搭載される。相互接続基板は半導体基板の表面積よりも小さい表面積を有している。   According to one aspect of the present invention, the present invention provides an integrated circuit package comprising a first plurality of bonding pads and a semiconductor in the integrated circuit package comprising a second plurality of bonding pads and having a surface area. An integrated circuit is provided that includes a substrate and a plurality of wire bonds connecting a selected one of the first plurality of bonding pads and a selected one of the second plurality of bonding pads. An interconnect substrate is mounted on the semiconductor substrate. The interconnect substrate has a surface area that is less than the surface area of the semiconductor substrate.

相互接続基板は半導体基板へとフリップチップボンディングにより取り付けることができる。相互接続基板は、有機材料、セラミック材料またはシリコン等の半導体から形成することができる。   The interconnect substrate can be attached to the semiconductor substrate by flip chip bonding. The interconnect substrate can be formed from an organic material, a ceramic material, or a semiconductor such as silicon.

相互接続基板は導電性の相互接続層を備えていることが望ましい。半導体基板は、相互接続基板を取り囲む周辺領域を有していることが望ましい。第二の複数のボンディングパッドの少なくとも一部は、その周辺領域中に設けることができる。相互接続基板は１つ以上のフィルタコンデンサ(filter capacitor)を更に備える場合がある。集積回路パッケージは空洞を備えていても良く、半導体基板をパッケージのその空洞中に接着することができる。   The interconnect substrate preferably includes a conductive interconnect layer. The semiconductor substrate preferably has a peripheral region surrounding the interconnect substrate. At least a portion of the second plurality of bonding pads can be provided in a peripheral region thereof. The interconnect substrate may further comprise one or more filter capacitors. The integrated circuit package may include a cavity, and a semiconductor substrate can be bonded into the cavity of the package.

集積回路パッケージは基板を備えていても良く、この場合は第一の複数のボンディングパッドおよび半導体基板が集積回路パッケージ基板上に設けられる。   The integrated circuit package may comprise a substrate, in which case a first plurality of bonding pads and a semiconductor substrate are provided on the integrated circuit package substrate.

本発明の更なる態様によれば、本発明は複数のボンディングパッドを備え、特定の表面積を有する半導体基板を備えた集積回路アセンブリを提供するものである。アセンブリは更に、半導体基板上にフリップチップボンディングされた相互接続基板も備えている。相互接続基板は半導体基板の表面積よりも小さい表面積を有している。   According to a further aspect of the invention, the present invention provides an integrated circuit assembly comprising a semiconductor substrate comprising a plurality of bonding pads and having a specific surface area. The assembly further includes an interconnect substrate that is flip-chip bonded onto the semiconductor substrate. The interconnect substrate has a surface area that is less than the surface area of the semiconductor substrate.

上述した態様および本発明に伴う利点は、以下の詳細説明を、添付図を参照しつつ読むことにより明らかとなる。   The aspects described above and the advantages associated with the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.

以下の説明は、当業者が本発明を実施および利用することが可能となるように提供するものである。本願に記載の一般原理は、本発明の精神および範囲から離れることなく、以下に記載する詳細説明以外の実施例および用途に適用することができる。本発明は、開示する実施例に限定されることを意図したものではなく、本願に開示または示唆される原理および特徴に合致する最も広い範囲に適用されるものである。   The following description is provided to enable any person skilled in the art to make and use the invention. The general principles described herein may be applied to embodiments and applications other than the detailed description set forth below without departing from the spirit and scope of the present invention. The present invention is not intended to be limited to the disclosed embodiments, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

図１は、本発明を実現した集積回路デバイス１０を示したものである。デバイス１０は一般に、パッケージ基板１２、半導体基板１４および相互接続基板１６を備えている。   FIG. 1 shows an integrated circuit device 10 embodying the present invention. Device 10 generally includes a package substrate 12, a semiconductor substrate 14, and an interconnect substrate 16.

パッケージ基板１２は当該分野において周知の多層基板であり、複数の導電性パターンを備えている。例えばパッケージ基板１２は、デバイス１０をプリント回路基板へと直接的に半田付けすることを容易にするために複数の半田ボール１８を備えている。パッケージ基板１２は、更に、当該分野において既知の方法でパッケージ基板１２上に取り付けられた第一の複数のボンディングパッド２０を備えている。   The package substrate 12 is a multilayer substrate well known in the art and includes a plurality of conductive patterns. For example, the package substrate 12 includes a plurality of solder balls 18 to facilitate soldering the device 10 directly to a printed circuit board. The package substrate 12 further includes a first plurality of bonding pads 20 attached on the package substrate 12 in a manner known in the art.

半導体基板１４は、接着剤２２により既知の方法でパッケージ基板１２へと接着されている。当該分野において周知のように、半導体基板１４は、周知のシャドウマスクおよび拡散技術を使ってその中で一体に形成された回路を備える場合もある。半導体基板１４は第二の複数のボンディングパッド２４を備えている。ボンディングパッド２４は、当該分野において周知の方法により半導体基板１４の相互接続層の各選択部へと結合されている。   The semiconductor substrate 14 is bonded to the package substrate 12 by an adhesive 22 by a known method. As is well known in the art, the semiconductor substrate 14 may comprise circuitry integrally formed therein using well known shadow mask and diffusion techniques. The semiconductor substrate 14 includes a second plurality of bonding pads 24. Bonding pad 24 is coupled to each selected portion of the interconnect layer of semiconductor substrate 14 by methods well known in the art.

相互接続基板１６は半導体基板１４へとフリップチップボンディングされている。このために相互接続基板は、複数の半田ボール２６を備えている。相互接続基板は有機材料、セラミック材料またはシリコン等の半導体材料から形成することができる。相互接続基板１６は、基板層上に形成された１層以上の導電性相互接続層２８を備えている。相互接続基板の複数の半田ボール２６は、半導体基板１４全体に電力とグラウンドを提供するために用いることができる。   Interconnect substrate 16 is flip-chip bonded to semiconductor substrate 14. For this purpose, the interconnect substrate is provided with a plurality of solder balls 26. The interconnect substrate can be formed from an organic material, a ceramic material, or a semiconductor material such as silicon. The interconnect substrate 16 includes one or more conductive interconnect layers 28 formed on the substrate layer. A plurality of solder balls 26 on the interconnect substrate can be used to provide power and ground to the entire semiconductor substrate 14.

図１に示すように、露出した周辺領域２９を作るために相互接続基板は半導体基板の表面積よりも小さい表面積を有している。半導体基板１４上に設けられる第二の複数のボンディングパッドの少なくとも一部は、この周辺領域２９中に設けられている。   As shown in FIG. 1, the interconnect substrate has a surface area that is less than the surface area of the semiconductor substrate to create an exposed peripheral region 29. At least a part of the second plurality of bonding pads provided on the semiconductor substrate 14 is provided in the peripheral region 29.

第一の複数のボンディングパッド２０の選択されたものが、半導体基板１４のボンディングパッド２４の選択されたものへと結合されており、電力とグラウンドを提供している。このためにデバイス１０は複数のボンディングワイヤ３０を備えており、これらがパッケージ基板１２のボンディングパッドが半導体基板１４のボンディングパッド２０へと当該分野において周知の方法により接続されている。よって電力およびグラウンドは、ワイヤボンド３０および外周にある半田ボール２６により相互接続基板１６へと供給されている。   A selected one of the first plurality of bonding pads 20 is coupled to a selected one of the bonding pads 24 of the semiconductor substrate 14 to provide power and ground. For this purpose, the device 10 includes a plurality of bonding wires 30, which are connected to bonding pads of the package substrate 12 to bonding pads 20 of the semiconductor substrate 14 by methods well known in the art. Thus, power and ground are supplied to the interconnect substrate 16 by wire bonds 30 and solder balls 26 on the outer periphery.

相互接続基板１６は複数のフィルタ素子３２を備えているが、これらは別個のコンデンサインダクタおよび／または抵抗器を備えている場合がある。フィルタ素子３２は電源電圧からノイズをフィルタするための、当該分野においては周知のタイプのものとすることができる。   The interconnect substrate 16 includes a plurality of filter elements 32, which may include separate capacitor inductors and / or resistors. The filter element 32 may be of a type well known in the art for filtering noise from the power supply voltage.

最後に、デバイス１０はデバイスの熱を放散させるためのヒートスプレッダ３４を備えている。ヒートスプレッダ３４の内部、およびヒートスプレッダ３４の外部には、デバイス用の環境障壁としての働きと同時に構造部品としての働きを持つ保護用化合物３６が設けられている。   Finally, the device 10 includes a heat spreader 34 for dissipating the heat of the device. Inside the heat spreader 34 and outside the heat spreader 34 is provided a protective compound 36 that functions as an environmental barrier for the device and at the same time functions as a structural component.

図２は、本発明を実現した他の集積回路デバイス５０を示す。デバイス５０はキャビティダウン構成と呼ばれるタイプのもので、デバイスパッケージは半導体基板５４をその中に受容する空洞５２を備えている。半導体基板５４は好適な接着剤５８によりパッケージ５６へと接着されている。   FIG. 2 shows another integrated circuit device 50 embodying the present invention. Device 50 is of a type referred to as a cavity-down configuration, and the device package includes a cavity 52 that receives a semiconductor substrate 54 therein. The semiconductor substrate 54 is bonded to the package 56 with a suitable adhesive 58.

パッケージ５６には基板６０が取り付けられている。基板６０は導電性の相互接続パターンを設けた多層基板であることが望ましい。基板６０は第一の複数のボンディングパッド６２を備えている。半導体基板５４には第二の複数のボンディングパッド６４が設けられている。半導体基板５４のボンディングパッドは、既知の方法により、ワイヤボンド６６を通じて基板６０のボンディングパッド６２へとワイヤボンディングされている。   A substrate 60 is attached to the package 56. The substrate 60 is preferably a multilayer substrate provided with conductive interconnect patterns. The substrate 60 includes a first plurality of bonding pads 62. A second plurality of bonding pads 64 are provided on the semiconductor substrate 54. The bonding pads of the semiconductor substrate 54 are wire bonded to the bonding pads 62 of the substrate 60 through wire bonds 66 by a known method.

相互接続基板７０は半導体基板５４上にある。相互接続基板７０は、複数の半田ボール７２により半導体基板５４へとフリップチップボンディングされる。更にワイヤボンド６７も選択されたパッド６２を接続している。相互接続基板７０は多層とすることができ、これにより半導体基板５４内における電源およびグラウンド配線がされている。   Interconnect substrate 70 is on semiconductor substrate 54. The interconnect substrate 70 is flip-chip bonded to the semiconductor substrate 54 with a plurality of solder balls 72. Further, the wire bond 67 connects the selected pad 62. The interconnect substrate 70 can be multi-layered so that power and ground wiring within the semiconductor substrate 54 are provided.

相互接続基板７０には電源電圧をフィルタするために複数のフィルタ素子７４が既知の方法で設けられている。ここでもフィルタ素子は別個のコンデンサ、インダクタおよび／または抵抗を有するものとすることができる。   The interconnect substrate 70 is provided with a plurality of filter elements 74 in a known manner for filtering the power supply voltage. Again, the filter element may have a separate capacitor, inductor and / or resistance.

半導体基板５４および相互接続基板７０のアセンブリは繊細なものであり、保護材または被包材７６により覆われていることが望ましい。被包材７６は当該分野において既知の方法により液体として吐出し、ダム７８を形成する更なる材料により特定の領域に閉じ込めることができる。ここでも相互接続基板７０の表面積は半導体基板５４の表面積よりも小さく、半導体基板のボンディングパッド６４を形成する周辺領域７３が作られている。   The assembly of semiconductor substrate 54 and interconnect substrate 70 is delicate and is preferably covered with a protective or encapsulating material 76. The encapsulant 76 can be ejected as a liquid by methods known in the art and confined to a specific area by additional material forming the dam 78. Again, the surface area of the interconnect substrate 70 is smaller than the surface area of the semiconductor substrate 54, creating a peripheral region 73 that forms the bonding pads 64 of the semiconductor substrate.

本発明の更なる態様によれば、図１に示した集積回路デバイスまたは図２に示した集積回路デバイスのいずれかにおいて、相互接続基板が電力およびグラウンド供給に加え、低インピーダンス経路または特殊フィルタリングを要する他の重要な信号の伝送に用いられる。電力、グラウンドおよび重要信号は、ワイヤボンディングまたは導電性相互接続層により、相互接続基板の相互接続部へと結合することができる。本発明の様々な態様に基づいて構成された集積回路は、パッケージ基板上の基板実装効率条件を低減しつつもデバイスの電気パフォーマンスを向上させるという２つの効果を持っている。基板のワイヤ密度条件はワイヤボンディングにより低下させつつも、フリップチップ搭載した相互接続基板と、オプションの個別コンデンサ、抵抗器および素子の利用により向上した電気パフォーマンスが提供されるのである。この結果、優良な電気パフォーマンスと低コストという二重の利点が得られるものである。   According to a further aspect of the present invention, in either the integrated circuit device shown in FIG. 1 or the integrated circuit device shown in FIG. 2, the interconnect substrate provides a low impedance path or special filtering in addition to power and ground supply. Used for transmission of other important signals required. Power, ground, and critical signals can be coupled to the interconnect substrate interconnects by wire bonding or conductive interconnect layers. An integrated circuit configured according to various aspects of the present invention has two effects of improving the electrical performance of the device while reducing the substrate mounting efficiency requirements on the package substrate. While the board wire density requirements are reduced by wire bonding, improved electrical performance is provided by the use of flip chip mounted interconnect substrates and optional individual capacitors, resistors and elements. This results in the dual advantage of good electrical performance and low cost.

本発明の第一の実施例に基づいて構成された集積回路を部分的に断面で示した側面図である。1 is a side view partially showing a cross-section of an integrated circuit configured according to a first embodiment of the present invention. 本発明の他の実施例に基づいて構成された集積回路を部分的に断面で示した側面図である。It is the side view which partially showed the integrated circuit comprised based on the other Example of this invention in the cross section.

符号の説明Explanation of symbols

１０ 集積回路
１４ 半導体基板
１６ 相互接続基板
２０ 第一のボンディングパッド
２４ 第二のボンディングパッド
２８ 相互接続層
２９ 周辺領域
３０ ワイヤボンド
３２ フィルタコンデンサ
５０ 集積回路
５４ 半導体基板
６２ 第一のボンディングパッド
６４ 第二のボンディングパッド
６６ ワイヤボンド
７０ 相互接続基板
７３ 周辺領域
７４ フィルタコンデンサ

DESCRIPTION OF SYMBOLS 10 Integrated circuit 14 Semiconductor substrate 16 Interconnect substrate 20 1st bonding pad 24 2nd bonding pad 28 Interconnect layer 29 Peripheral area 30 Wire bond 32 Filter capacitor 50 Integrated circuit 54 Semiconductor substrate 62 1st bonding pad 64 2nd Bonding pad 66 wire bond 70 interconnect substrate 73 peripheral area 74 filter capacitor

Claims (6)

第一の複数のボンディングパッドを有する第一の基板を備え、該第一の基板が配置された表面側に開口する空洞が設けられた集積回路パッケージと、
前記集積回路パッケージの前記空洞に配置された半導体基板であって、該半導体基板は、第二の複数のボンディングパッドを備えると共に、ある表面積を有しており、前記半導体基板の第一の面は、前記空洞内に配置され、前記半導体基板における前記第一の面と反対側に位置する第二の面は、前記集積回路パッケージの表面と略同一平面上になるように配置されている、半導体基板と、
前記第一の複数のボンディングパッドから選択されたものを前記第二の複数のボンディングパッドの選択されたものへと接続する複数のワイヤボンドと、
前記半導体基板上に取り付けられ、前記半導体基板の前記表面積よりも小さい表面積を有し、前記半導体基板へフリップチップボンディングされており、及び前記第一の複数のボンディングパッドから選択されたものが複数のワイヤボンドにより接続されている、相互接続基板と
を備えたことを特徴とする集積回路。 An integrated circuit package comprising a first substrate having a first plurality of bonding pads, and provided with a cavity opening on the surface side where the first substrate is disposed;
A semiconductor substrate disposed in the cavity of the integrated circuit package, the semiconductor substrate comprising a second plurality of bonding pads and having a certain surface area, the first surface of the semiconductor substrate being The second surface disposed in the cavity and located on the opposite side to the first surface of the semiconductor substrate is disposed so as to be substantially flush with the surface of the integrated circuit package. A substrate,
A plurality of wire bonds connecting a selected one of the first plurality of bonding pads to a selected one of the second plurality of bonding pads;
Wherein mounted on the semiconductor substrate, said to have a smaller surface area than the surface area of the semiconductor substrate, said semiconductor substrate being flip-chip bonding to, and those selected from the first plurality of bonding pads is plural An integrated circuit comprising an interconnect substrate connected by wire bonds . 前記相互接続基板が、有機材料、セラミックおよびシリコンのうちの１つから形成されていることを特徴とする、請求項１に記載の集積回路。 The integrated circuit of claim 1, wherein the interconnect substrate is formed from one of an organic material, ceramic, and silicon. 前記相互接続基板が、その上に導電性の相互接続層を備えていることを特徴とする、請求項１又は請求項２に記載の集積回路。 The integrated circuit according to claim 1 or 2, wherein the interconnect substrate comprises a conductive interconnect layer thereon. 前記半導体基板が、前記相互接続基板を取り囲む周辺領域を有し、前記第二の複数のボンディングパッドの少なくとも一部が、前記周辺領域中にあることを特徴とする、請求項１から請求項３のいずれかに記載の集積回路。 Said semiconductor substrate has a peripheral region surrounding the interconnect substrate, at least a portion of said second plurality of bonding pads, characterized in that in the peripheral region, claims 1 to 3 An integrated circuit according to any one of the above. 前記相互接続基板が、少なくとも１つのフィルタコンデンサを備えていることを特徴とする、請求項１から請求項４のいずれかに記載の集積回路。 It said interconnection board, characterized in that it comprises at least one filter capacitor, integrated circuit according to any one of claims 1 to 4. 前記相互接続基板及び前記集積回路パッケージ上の前記第一の基板が、略同一平面上になるように配置されていることを特徴とする請求項１から請求項５のいずれかに記載の集積回路。 Said first substrate on said interconnect board and the integrated circuit package, the integrated circuit according to are arranged to be generally coplanar claim 1, wherein in any one of claims 5 .
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