CN110828496B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN110828496B CN110828496B CN201911119139.7A CN201911119139A CN110828496B CN 110828496 B CN110828496 B CN 110828496B CN 201911119139 A CN201911119139 A CN 201911119139A CN 110828496 B CN110828496 B CN 110828496B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
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- UFNIBRDIUNVOMX-UHFFFAOYSA-N 2,4'-dichlorobiphenyl Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC=C1Cl UFNIBRDIUNVOMX-UHFFFAOYSA-N 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/1469—Assemblies, i.e. hybrid integration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: s1, arranging a required number of groove bodies on the front side of a silicon substrate; s2, thinning the wafers of the first chip and the second chip to the required thickness; s3, respectively fixing the first chip and the second chip in the groove body; s4, welding spots are arranged on the solder mask layers on the surface layers of the first chip and the second chip; and S5, thinning the back surface of the silicon substrate, and then welding the third chip on the set welding points in a flip-chip mode. According to the manufacturing method of the semiconductor device, the first chip and the second chip are packaged through the silicon substrate, the third chip is connected with the first chip and the second chip in an inverted mode, the final packaging thickness is smaller than 600 micrometers, ultrathin packaging with smaller volume is achieved, three-dimensional interconnection is achieved, and the signal transmission distance is longer and faster.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
The image sensor utilizes the photoelectric conversion function of the photoelectric device. The light image on the light sensing surface is converted into an electric signal in corresponding proportion to the light image. In contrast to the photosensitive elements of "point" light sources such as photodiodes, phototransistors, etc., image sensors are functional devices that divide the light image on their light-receiving surface into many small cells and convert it into usable electrical signals.
The chip related to the image sensing technology includes: CMOS chips, ISP chips and DDR chips. At present, the image sensor package is to place the CMOS chip, the ISP chip and the DDR chip on the PCB. However, in the above-mentioned packaging method, the signal is led out by a wire bonding method, and the conventional packaging method of the image sensor has the problems of large packaging volume and thick packaging thickness. Therefore, it is necessary to provide a further solution to the above-mentioned problems.
Disclosure of Invention
The present invention is directed to a semiconductor device and a method for manufacturing the same to overcome the disadvantages of the prior art.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a semiconductor device manufacturing method, comprising the steps of:
s1, arranging a required number of groove bodies on the front surface of a silicon substrate;
s2, thinning the wafers of the first chip and the second chip to a required thickness;
s3, respectively fixing the first chip and the second chip in the groove body;
s4, welding spots are arranged on the solder mask layers on the surface layers of the first chip and the second chip;
and S5, thinning the back surface of the silicon substrate, and then welding the third chip on the arranged welding points in an inverted mode.
As a manufacturing method of the semiconductor device manufacturing method of the present invention, the step S2 specifically includes: firstly, the wafers of the first chip and the second chip are thinned to the required thickness, and then the thinned wafers are cut to form single chips.
As a manufacturing method of the semiconductor device manufacturing method of the present invention, the step S2 specifically includes: cutting to form a single chip, and thinning the wafer of the single first chip and the single second chip to the required thickness.
In the manufacturing method of the semiconductor device according to the present invention, in step S3, the first chip and the second chip are adhered to the bottom surface of the groove body by using an adhesive.
As a manufacturing method of the semiconductor device manufacturing method of the present invention, in the step S3, a passivation layer is formed on the surfaces of the first chip and the second chip and the gaps between the first chip and the groove, and the bonding position of the chip is formed on the passivation layer.
As a manufacturing method of the semiconductor device manufacturing method of the present invention, between steps S3 and S4, the method further includes: and the signals of the first chip and the second chip are led out in a rewiring mode.
As a manufacturing method of a semiconductor device manufacturing method of the present invention, the rewiring is a metal rewiring including: and depositing a seed layer at the welding position of the first chip and the second chip, photoetching a circuit, and thickening the metal circuit to the required thickness.
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, wherein the rewiring is a multilayer metal rewiring including: and depositing a seed layer by layer at the welding position of the first chip and the second chip, photoetching a circuit while depositing, and forming a protective layer on the last layer of circuit by adopting a chemical plating mode.
As a manufacturing method of a semiconductor device manufacturing method of the present invention, the semiconductor device manufacturing method further includes:
and S6, cutting the product obtained in the step S5 to obtain single packaging bodies, and welding the single packaging bodies to the PCB in a routing mode.
As a manufacturing method of the semiconductor device manufacturing method of the present invention, the first chip is an ISP chip, the second chip is a DDR chip, and the third chip is a CMOS chip.
In order to solve the technical problem, the technical scheme of the invention is as follows:
a semiconductor device obtained by the semiconductor device manufacturing method as described above, the semiconductor device having an overall package thickness of less than 600um.
Compared with the prior art, the invention has the beneficial effects that: according to the manufacturing method of the semiconductor device, the first chip and the second chip are packaged through the silicon substrate, the third chip is connected with the first chip and the second chip in an inverted mode, the final packaging thickness is smaller than 600 micrometers, ultrathin packaging with smaller volume is achieved, three-dimensional interconnection is achieved, and the signal transmission distance is longer and faster.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 to 4 are process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The semiconductor device manufacturing method of the present invention can be applied to packaging of a semiconductor device having three or more chips. For example, it is applicable to an ultra-thin package of an image sensor. Wherein the image sensor includes: the CMOS chip, the ISP chip and the DDR chip realize ultrathin packaging with smaller volume, three-dimensional interconnection and longer and faster signal transmission distance by the manufacturing method of the semiconductor device.
The method for manufacturing a semiconductor device of the present invention comprises the steps of:
s1, arranging a required number of groove bodies on the front surface of a silicon substrate;
s2, thinning the wafers of the first chip and the second chip to a required thickness;
s3, respectively fixing the first chip and the second chip in the groove body;
s4, welding spots are arranged on the solder mask layers on the surface layers of the first chip and the second chip;
and S5, thinning the back surface of the silicon substrate, and then welding the third chip on the set welding points in a flip-chip mode.
With respect to the above steps, the following description is made of the technical solution of the package of the image sensor in combination with the embodiment of the image sensor.
As shown in fig. 1, for step S1.
The groove body 11 is etched on the front side of the silicon substrate 1 in an etching mode, and the groove depth can be etched to different depths according to the packaging requirements. The number of the troughs 11 is determined by the number of the embedded ISP chips and DDR chips.
As shown in fig. 2, for step S2.
The wafers of the ISP chip 2 and the DDR chip 3 are thinned to a required thickness, and two parallel embodiments can be specifically adopted.
In one embodiment, the wafers of the ISP chip 2 and the DDR chip 3 are thinned to a required thickness, and then the thinned wafers are cut to form single chips. In another embodiment, a single chip is formed by cutting, and then the wafer of the single ISP chip 2 and the single DDR chip 3 is thinned to the required thickness. Through the processing mode of the thinning and cutting, the final packaging thickness is favorably smaller than 600um.
Step S3 is directed.
The ISP chip 2 and the DDR chip 3 are adhered to the bottom surface of the groove body 11 in an adhesive way. The above-mentioned bonding can be achieved, for example, by means of a DAF film or by means of a printed glue.
The step S3 further includes: and forming a passivation layer 4 on the surfaces of the ISP chips 2 and the DDR chips 3 and the gaps between the ISP chips 2 and the DDR chips 3 and the groove bodies 11, and forming a welding position of the chips on the passivation layer 4. For example, the passivation layer 4 is formed on the chip surface by vacuum lamination, the gap between the chip and the slot 11 is filled, and the bonding position of the chip is opened by exposure and development.
In addition, between the steps S3 and S4, the method further includes: signals of the ISP chip 2 and the DDR chip 3 are led out in a rewiring mode.
In one embodiment, the rewiring is a metal rewiring, which includes: a seed layer 5, such as Ti/Cu, al and the like, is deposited at the welding position of the ISP chip 2 and the DDR chip 3, then a circuit is photoetched, and then the metal circuit is thickened to the required thickness.
In another embodiment, for a product with a high density of I/O interfaces, a multi-layer wiring scheme may be used. In this case, the rewiring method is a multilayer metal rewiring including: and depositing a seed layer 5 layer by layer at the welding position of the ISP chip 2 and the DDR chip 3, photoetching a circuit while depositing, and forming a protective layer on the last layer of circuit by adopting a chemical plating mode to prevent the corrosion of the metal circuit.
Step S4 is followed. The solder resist layer 6 is formed on the surface layer of the chip for the purpose of preventing moisture from entering.
As shown in fig. 3, for step S5. When the CMOS chip 7 is welded on the welding spot in an inverted mode, ultra-thin glass 100-200um is used for bonding, ultra-thin packaging is achieved through the TSV technology, and the total packaging thickness is smaller than 600um.
As shown in fig. 4, the semiconductor device manufacturing method further includes:
and S6, cutting the product obtained in the step S5 to obtain single packaging bodies, and welding the single packaging bodies to the PCB 8 in a routing mode.
The invention also provides a semiconductor device based on the manufacturing method of the semiconductor device.
At this time, the semiconductor device is obtained by the semiconductor device manufacturing method as described above, and the overall package thickness of the semiconductor device is less than 600um. When the first chip is an ISP chip, the second chip is a DDR chip, the third chip is a CMOS chip, and the semiconductor device is an image sensor.
In summary, in the manufacturing method of the semiconductor device of the present invention, the first chip and the second chip are packaged by the silicon substrate, and the third chip and the first chip and the second chip are interconnected by the flip chip, and the final package thickness is smaller than 600um, so that the ultrathin and smaller package is realized, the three-dimensional interconnection is realized, and the signal transmission distance is longer and faster.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it is to be understood that all embodiments may be combined as appropriate by one of ordinary skill in the art to form other embodiments as will be apparent to those of skill in the art from the description herein.
Claims (9)
1. A semiconductor device manufacturing method, characterized by comprising the steps of:
s1, arranging a required number of groove bodies on the front side of a silicon substrate;
s2, thinning the wafers of the first chip and the second chip to the required thickness;
the step S2 specifically includes: firstly, thinning the wafers of the first chip and the second chip to the required thickness, and then cutting the thinned wafers to form single chips; or; the step S2 specifically includes: cutting to form a single chip, and thinning the wafer of the single first chip and the wafer of the single second chip to the required thickness;
s3, respectively fixing the first chip and the second chip in the groove body;
s4, welding spots are arranged on the solder mask layers on the surface layers of the first chip and the second chip;
s5, thinning the back surface of the silicon substrate, and welding a third chip on the set welding spot in an inverted mode;
the first chip is an ISP chip, the second chip is a DDR chip, and the third chip is a CMOS chip; the DDR chip is respectively arranged on two sides of the ISP chip; and when the CMOS chip is welded on the welding points in an inverted mode, ultra-thin glass 100-200um is used for bonding, ultra-thin packaging is realized through the TSV technology, and the total packaging thickness is smaller than 600um.
2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step S3, the first chip and the second chip are adhered to the bottom surface of the groove body by an adhesive method.
3. The manufacturing method of the semiconductor device according to claim 1 or 2, wherein in the step S3, a passivation layer is formed on the surfaces of the first chip and the second chip and the gaps between the first chip and the groove body and between the second chip and the groove body, and the bonding position of the chip is formed on the passivation layer.
4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein between the steps S3 and S4, further comprising: and signals of the first chip and the second chip are led out in a rewiring mode.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the rewiring is a metal rewiring including: and depositing a seed layer at the welding position of the first chip and the second chip, photoetching a circuit, and thickening the metal circuit to the required thickness.
6. The method for manufacturing a semiconductor device according to claim 4, wherein the rewiring is a multilayer metal rewiring comprising: and depositing a seed layer by layer at the welding position of the first chip and the second chip, photoetching a circuit while depositing, and forming a protective layer on the last layer of circuit by adopting a chemical plating mode.
7. The semiconductor device manufacturing method according to claim 1, further comprising:
and S6, cutting the product obtained in the step S5 to obtain single packaging bodies, and welding the single packaging bodies to the PCB in a routing mode.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the first chip is an ISP chip, the second chip is a DDR chip, and the third chip is a CMOS chip.
9. A semiconductor device obtained by the method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that the overall package thickness of the semiconductor device is less than 600um.
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| CN103943605A (en) * | 2014-03-31 | 2014-07-23 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure and method based on ultra-thin glass |
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