CN109786368A - A kind of photoelectric chip collaboration encapsulating structure and method - Google Patents
A kind of photoelectric chip collaboration encapsulating structure and method Download PDFInfo
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- CN109786368A CN109786368A CN201910068155.1A CN201910068155A CN109786368A CN 109786368 A CN109786368 A CN 109786368A CN 201910068155 A CN201910068155 A CN 201910068155A CN 109786368 A CN109786368 A CN 109786368A
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- 230000003287 optical effect Effects 0.000 claims description 9
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- 238000005538 encapsulation Methods 0.000 abstract description 18
- 238000004519 manufacturing process Methods 0.000 abstract description 14
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The present invention provides a kind of photoelectric chip collaboration encapsulating structure and method, the encapsulating structure include the wafer for being provided with photon chip, on the wafer for be provided with photon chip and is located at photon chip side and is equipped with cavity, and electrical chip is just being put in the cavity；The structure further includes metal wiring layer for connecting respectively with electrical chip pad, photon chip pad, is arranged on the metal wiring layer and for by the photon chip, electrical chip and the extraneous convex block or soldered ball being electrically attached.The present invention can directly integrate electrical chip and photon chip in photon chip manufacturing process, realize the collaboration encapsulation of wafer scale light, electrical chip, the step of avoiding conventional package from encapsulating electrical chip and photon chip respectively, suitable for batch production, reduce processing step compared with traditional light, electrical chip collaboration packaging technology, keep technique simpler, saves production cost.
Description
Technical field
The present invention relates to technical field of photo communication more particularly to a kind of photoelectric chip collaboration encapsulating structure and methods.
Background technique
Due to the needs of cloud computing and being widely used for mobile device, explosive increasing is being presented in the data traffic in network
Long, the data transmission capacity needs of especially data center are sharply increased to handle these a large amount of data, so currently, full generation
Boundary is all in research and development optic communication energetically.With the gradually development of science and technology, people chase after to the signaling rate of optic communication
Ask also higher and higher.At the same time, people also increasingly pay attention to the encapsulation of light, electrical chip, currently, the association of light, electrical chip
Important research topic has been increasingly becoming with encapsulation.
In existing light, electrical chip collaboration encapsulation, the general packaged type for using traditional die, by electrical chip and photon
Flip-chip realizes that electrical connection or electrical chip and photon chip are welded on substrate by convex block or soldered ball on substrate
On, it is connected on substrate by the way of bonding line.This traditional light, electrical chip collaboration packaging method not only occupy more
Area, be unsatisfactory for the demand for development of small-sized package, and be also limited by the influence of transmission rate.In addition, electrical chip and light
Sub- chip needs first respectively fixed to the signal transmission that could realize light, electrical chip on substrate on substrate, and encapsulation process is complicated, no
It is suitable for mass production.
Patent CN108091629A describes another light, electrical chip packaging method, and electricity (light) chip is placed upside down in substrate
On, light (electricity) chip formal dress in addition is placed, and the pad of the two is corresponding, realizes photon chip and electrical chip by soldered ball
Electrical connection, shorten signal transmission path.But this method needs the pad by photon chip and electrical chip accurately right
Standard brings certain difficulty to encapsulation process, is not suitable for mass production.
Summary of the invention
Photoelectric chip collaboration encapsulating structure provided by the invention and method, can be directly in photon chip manufacturing process
In just electrical chip and photon chip are integrated, realize wafer scale light, electrical chip collaboration encapsulation, avoid conventional package by battery core
The step of piece and photon chip encapsulate respectively is suitable for batch production, reduces compared with traditional light, electrical chip collaboration packaging technology
Processing step, keeps technique simpler, has saved production cost.
In a first aspect, the present invention provides a kind of photoelectric chip collaboration encapsulating structure, the wafer including being provided with photon chip,
On the wafer for be provided with photon chip and it is located at photon chip side equipped with cavity, and electrical chip is just being placed on to the cavity
It is interior；
The structure further includes metal wiring layer for connecting respectively with electrical chip pad, photon chip pad, setting
Convex block or soldered ball on the metal wiring layer and for the photon chip, electrical chip and the external world to be electrically attached.
Optionally, the size of the cavity is corresponding with the size of the electrical chip so that by the electrical chip pad with
Photon chip pad locations are concordant.
Optionally, the electrical chip is welded using conductive material and cavity bottom；
Alternatively, the cavity bottom is connected by the surface of deposited metal and wafer.
Optionally, when the photon chip is edge emitting or received laser, detector or modulator, then the structure
It further include the groove for being arranged in the wafer substrate of photon chip transmitting or receiving end side and being used for optical signal transmission.
Optionally, the cavity and the groove, which are cooperateed with using photoetching or etching technics in the wafer-level photoelectric chip, seals
Processing is formed in assembling structure.
Optionally, the structure further includes the light-sensitive material being covered on wafer, and by electrical chip pad and photon
Windowing wiring is carried out to light-sensitive material at chip bonding pad and forms metal wiring layer.
Second aspect, the present invention provide a kind of photoelectric chip collaboration packaging method, comprising:
On the wafer for be provided with photon chip and it is located at photon chip side setting cavity, and electrical chip is just being placed on to institute
It states in cavity；
Metal wiring layer of the setting for being connect respectively with electrical chip pad, photon chip pad on wafer；
Setting is convex for the photon chip, electrical chip to be electrically attached with the external world on the metal wiring layer
Block or soldered ball；
It is cut to as at least one electrical chip and unit composed by least one photon chip, and forms wafer scale
Photoelectric chip cooperates with encapsulating structure.
Optionally, the size of the cavity is corresponding with the size of the electrical chip so that by the electrical chip pad with
Photon chip pad locations are concordant.
Optionally, the electrical chip is welded using conductive material and cavity bottom；
Alternatively, the cavity bottom is connected by the surface of deposited metal and wafer.
Optionally, described, setting is used for the metal connecting respectively with electrical chip pad, photon chip pad on wafer
After wiring layer, the method also includes:
When the photon chip is edge emitting or received laser, detector or modulator, then sent out in photon chip
Penetrate or the wafer substrate of receiving end side on setting be used for optical signal transmission groove；
Preferably, the cavity and the groove, which are cooperateed with using photoetching or etching technics in the wafer-level photoelectric chip, seals
Processing is formed in assembling structure.
Photoelectric chip collaboration encapsulating structure provided in an embodiment of the present invention and method, the encapsulating structure is mainly in wafer
The empty cavity of upper setting, and by photon chip and electrical chip collaboration encapsulation by way of being embedded to electrical chip in cavity body, no
It is same as conventional package electrical chip and photon chip distribution are inverted on substrate, electrical connection is realized by convex block or soldered ball,
Collaboration encapsulating structure described in the present embodiment installs electrical chip, Jin Erneng by the way that cavity is arranged in the wafer for being provided with photon chip
It is enough directly just to integrate electrical chip and photon chip in photon chip manufacturing process, so that the size of the encapsulating structure
It is smaller, meet the demand for development of small-sized package.
Meanwhile the present embodiment realizes the collaboration encapsulation of wafer scale light, electrical chip, avoid conventional package by electrical chip and
The step of photon chip encapsulates respectively is suitable for batch production, reduces work compared with traditional light, electrical chip collaboration packaging technology
Skill step keeps technique simpler, has saved production cost.In addition, encapsulating structure described in the present embodiment can also pass through utilization
Accurate photoetching process realizes that digging chamber step carrys out integrated power chips, avoids packaged electrical chip and photon in conventional package
Processing step of the flip-chip on substrate, also more traditional light, electrical chip collaboration encapsulate for the mechanical performance for making encapsulation and electrical property
It is significantly improved.
Detailed description of the invention
Fig. 1 is the flow chart that one embodiment of the invention photoelectric chip cooperates with packaging method；
Fig. 2 is the structural schematic diagram that cavity is arranged in one embodiment of the invention on the wafer for be provided with photon chip；
Fig. 3 is the structural schematic diagram that one embodiment of the invention places electrical chip in the cavity；
Fig. 4 is the structure that another embodiment of the present invention covers light-sensitive material on the wafer with electrical chip, photon chip
Schematic diagram；
Fig. 5 is the structural schematic diagram after another embodiment of the present invention opens a window to light-sensitive material；
Fig. 6 is the knot that metal wiring layer is arranged in another embodiment of the present invention on the wafer with electrical chip, photon chip
Structure schematic diagram；
Fig. 7 is the knot that convex block or soldered ball is arranged in another embodiment of the present invention on the wafer with electrical chip, photon chip
Structure schematic diagram；
Fig. 8 is another embodiment of the present invention to the unit as composed by least one electrical chip and at least one photon chip
The structural schematic diagram cut；
Wherein, 1, convex block or soldered ball；2, electrical chip；3, cavity；4, metal wiring layer；5, chip bonding pad；6, photon chip；
7, light-sensitive material；8, photon chip substrate；9, V-groove.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of photoelectric chip collaboration encapsulating structure, as shown in figure 8, the structure includes being provided with
The wafer of photon chip 6 on the wafer for being provided with photon chip 6 and is located at photon chip side and is equipped with cavity 3, and by battery core
Piece 2 is just being placed in the cavity 3；
The structure further includes metal wiring layer for connecting respectively with electrical chip pad 5, photon chip pad 5, sets
It sets on the metal wiring layer 4 and is used for the photon chip, electrical chip and the extraneous convex block being electrically attached or weldering
Ball 1.
Photoelectric chip collaboration encapsulating structure provided in an embodiment of the present invention is mainly the cavity 3 that sky is arranged on wafer, and
By photon chip 6 and the collaboration encapsulation of electrical chip 2 by way of being embedded to electrical chip 2 in cavity body 3, being different from conventional package will
Electrical chip 2 and the distribution of photon chip 6 are inverted on substrate, electrical connection are realized by convex block or soldered ball 1, described in the present embodiment
It cooperates with encapsulating structure that electrical chip 2 is installed by the way that cavity 3 is arranged in the wafer for being provided with photon chip 6, and then can directly exist
Just electrical chip 2 and photon chip 6 are integrated in 6 manufacturing process of photon chip, so that the encapsulating structure is smaller,
Meet the demand for development of small-sized package.
Meanwhile the present embodiment realizes the collaboration encapsulation of wafer scale light, electrical chip, avoids conventional package for electrical chip 2
The step of encapsulating respectively with photon chip 6 is suitable for batch production, reduces compared with traditional light, electrical chip collaboration packaging technology
Processing step, keeps technique simpler, has saved production cost.In addition, encapsulating structure described in the present embodiment can also pass through
It is realized using accurate photoetching process and digs chamber step come integrated power chips, avoided packaged electrical chip 2 in conventional package
It is inverted in the processing step on substrate with photon chip 6, the mechanical performance and electrical property for making encapsulation also assist by more traditional light, electrical chip
It is significantly improved with encapsulation.
Optionally, as illustrated in figs. 2 through 8, the size of the cavity 3 is corresponding with the size of the electrical chip 2, so that by institute
It is concordant with photon chip pad locations to state electrical chip pad.
Optionally, the electrical chip 2 is welded using conductive material and cavity bottom；
Alternatively, the cavity bottom is connected by the surface of deposited metal and wafer.
Optionally, when the photon chip 6 is edge emitting or received laser, detector or modulator, then the knot
Structure further includes the groove for being arranged in the wafer substrate of the transmitting of photon chip 8 or receiving end side and being used for optical signal transmission；Its
In, the wafer substrate is as photon chip substrate 8.
Optionally, the cavity 3 and the groove are cooperateed with using photoetching or etching technics in the wafer-level photoelectric chip
Processing is formed in encapsulating structure.
Specifically, cavity described in the present embodiment can be used for integrated power chips in 8 structure of wafer scale photon chip substrate
In, form a kind of novel wafer grade photoelectric chip collaboration encapsulating structure；The photon chip electrical chip is located at wafer stage chip envelope
In assembling structure and form wafer-level photoelectric chip collaboration encapsulating structure；And in the wafer-level photoelectric chip collaboration encapsulating structure
Including at least a photon chip 6 and an electrical chip 2, and then can realize battery core directly in 6 manufacture craft of photon chip
Piece 2 is integrated to form wafer-level photoelectric chip with photon chip 6 and cooperates with encapsulating structure, reduces encapsulating structure size, meets small
The demand for development of sized package.
Meanwhile the cavity, groove are cooperateed in encapsulating structure using photoetching, etching technics in the wafer-level photoelectric chip
It is formed；The groove may be configured as U-type groove or V-groove 9 or ladder-type trough.Also, 3 bottom of cavity can pass through deposited metal etc.
It is connect with the surface of wafer, realizes electric interconnection, in addition, conductive material can be used for the electrical chip 2 and cavity bottom welding connects
It connects；So that the performance of electrical chip 2 and the performance of photoelectric chip are effectively promoted in encapsulating structure.
In addition, the electrical chip 2 can be driving chip (Driver), trans-impedance amplifier chip (TIA), clock recovery core
Piece, bias chip, singlechip chip, other control chips.
Optionally, the structure further includes the light-sensitive material 7 being covered on wafer, and by 2 pad of electrical chip and light
Windowing wiring is carried out to light-sensitive material 7 at sub- 6 pad of chip and forms metal wiring layer 4.
Specifically, the collaboration encapsulating structure of photoelectric chip described in the present embodiment can be between metal wiring layer 4 and crystal column surface
Light-sensitive material 7 is set, windowing wiring setting metal wiring layer 4 is then carried out on light-sensitive material 7, is guaranteeing photoelectric chip collaboration
While encapsulating structure performance, the photon chip 6, electrical chip 2 and extraneous electrical connection are realized.
The embodiment of the present invention also provides a kind of photoelectric chip collaboration packaging method, as shown in Figures 1 to 8, the method packet
It includes:
S11, on the wafer for being provided with photon chip 6 and it is located at 6 side of photon chip cavity 3 is set, and by electrical chip 2
It is just being placed in the cavity 3；
S12, metal wiring layer 4 of the setting for being connect respectively with electrical chip pad 5, photon chip pad 5 on wafer；
S13, it is arranged on the metal wiring layer 4 for electrically carrying out the photon chip 6, electrical chip 2 and the external world
The convex block or soldered ball 1 of connection；
S14, it cuts, and is formed to as at least one electrical chip 2 and unit composed by least one photon chip 6
Wafer-level photoelectric chip cooperates with encapsulating structure.
Photoelectric chip collaboration packaging method provided in an embodiment of the present invention is mainly the cavity 3 that sky is arranged on wafer, and
By photon chip 6 and the collaboration encapsulation of electrical chip 2 by way of being embedded to electrical chip 2 in cavity body 3, being different from conventional package will
Electrical chip 2 and the distribution of photon chip 6 are inverted on substrate, electrical connection are realized by convex block or soldered ball 1, described in the present embodiment
Method installs electrical chip 2 by the way that cavity 3 is arranged in the wafer for being provided with photon chip 6, and then can be directly in photon chip 6
Just electrical chip 2 and photon chip 6 are integrated in manufacturing process, so that the encapsulating structure is smaller, met small
The demand for development of sized package.
Meanwhile the present embodiment realizes the collaboration encapsulation of wafer scale light, electrical chip, avoids conventional package for electrical chip 2
The step of encapsulating respectively with photon chip 6 is suitable for batch production, reduces compared with traditional light, electrical chip collaboration packaging technology
Processing step, keeps technique simpler, has saved production cost.In addition, the present embodiment the method can also pass through utilization
Accurate photoetching process realizes that digging chamber step carrys out integrated power chips, avoids packaged electrical chip and photon in conventional package
Processing step of the flip-chip on substrate, also more traditional light, electrical chip collaboration encapsulate for the mechanical performance for making encapsulation and electrical property
It is significantly improved.
Optionally, the size of the cavity 3 is corresponding with the size of the electrical chip 2, so that by the electrical chip pad
It is concordant with photon chip pad locations.
Optionally, the electrical chip 2 is welded using conductive material and 3 bottom of cavity；
Alternatively, 2 bottom of chamber is connected by the surface of deposited metal and wafer.
Optionally, described, setting is used for the metal connecting respectively with electrical chip pad, photon chip pad 5 on wafer
After wiring layer 4, the method also includes:
When the photon chip 6 is edge emitting or received laser, detector or modulator, then sent out in photon chip
Penetrate or the wafer substrate of receiving end side on setting be used for optical signal transmission groove；
Optionally, the groove may be configured as U-type groove or V-groove 9 or ladder-type trough.
Preferably, the cavity 3 and the groove are cooperateed with using photoetching or etching technics in the wafer-level photoelectric chip
Processing is formed in encapsulating structure.
In conclusion the method includes making steps for the present embodiment:
(1): preparing wafer, production has photon chip 6 in the wafer；Wherein, the wafer is silicon materials or GaAs
Substrate material or other materials；
(2): as shown in Figure 1, chamber 3,3 size of cavity and the electricity to be embedded to is arranged in 6 side of photon chip
2 size of chip is identical；Wherein, the electrical chip 2 can be extensive for driving chip (Driver), trans-impedance amplifier chip (TIA), clock
Multiple chip, bias chip, singlechip chip, other control chips；
(3): when the photon chip 6 is edge emitting or received laser, detector or modulator, then in photon core
Setting is used for the V-shaped slot 9 of optical signal transmission in the wafer substrate of piece transmitting or receiving end side；
Alternatively, being then not provided with when the photon chip 6 is surface launching or received laser, detector or modulator
For optical signal transmission V-shaped slot 9 and be directly set and carry out optical signal transmission in the transmitting on photon chip surface or receiving end；
(4): as shown in Fig. 2, placing electrical chip 2 in the cavity, electrical chip 2 is just put, electrical chip pad and photon core
Piece pad 5 is concordant, and solder sheet can be used in electrical chip 2 and cavity bottom is welded；
(5): as shown in figure 3, making light-sensitive material 7 on the wafer；
(6): as shown in figure 4, in 7 uplifting window of light-sensitive material；
(7): as shown in figure 5, forming the metal wiring layer at 7 uplifting window of light-sensitive material and on light-sensitive material 7
4, the metal wiring layer 4 is connect with the photon chip pad 5, electrical chip pad 5 respectively；
(8): as shown in fig. 6, making convex block or soldered ball 1, the convex block or soldered ball 1 on the metal wiring layer makes chip
Pad 5 and extraneous realize are electrically connected；
(9): the electrical chip and photon chip unit are cut, wherein laser technology can be used in the wafer
Grade chip-packaging structure inscribe, which is cut into single electrical chip and photon chip unit and forms wafer-level photoelectric chip and cooperate with, encapsulates knot
Structure；
In addition, photoetching or etching technics, which can be used, in the cavity and V-shaped slot 9 cooperates with encapsulation in the wafer-level photoelectric chip
It is formed in structure；And the photon chip 6, electrical chip 2 are located in wafer-level photoelectric chip collaboration encapsulating structure, meanwhile, institute
It states wafer-level photoelectric chip collaboration encapsulating structure and includes at least a photon chip 6 and an electrical chip 2；
Optionally, the photon chip 6 is edge emitting or received laser, detector or modulator.
Optionally, the electrical chip 2 can be driving chip (Driver), trans-impedance amplifier chip (TIA), clock recovery core
Piece, bias chip, singlechip chip, other control chips.
Optionally, there are the pad of connection chip internal circuits, chip weldering in the photon chip 6 and 2 upper surface of electrical chip
Disk 5 and the metal wiring layer 4 realize internal connection.
The method of the present embodiment can be used for preparing the technical solution of above structure embodiment, realization principle and technology
Effect is similar, and details are not described herein again.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of photoelectric chip cooperates with encapsulating structure, which is characterized in that the wafer including being provided with photon chip is being provided with light
On the wafer of sub- chip and it is located at photon chip side equipped with cavity, and electrical chip is just being put in the cavity；
The structure further includes metal wiring layer for connecting respectively with electrical chip pad, photon chip pad, is arranged in institute
State the convex block or soldered ball on metal wiring layer and for the photon chip, electrical chip and the external world to be electrically attached.
2. structure according to claim 1, which is characterized in that the size of the cavity is opposite with the size of the electrical chip
It answers, so that the electrical chip pad is concordant with photon chip pad locations.
3. structure according to claim 1 or 2, which is characterized in that the electrical chip uses conductive material and cavity bottom
Welding；
Alternatively, the cavity bottom is connected by the surface of deposited metal and wafer.
4. structure according to claim 1 to 3, which is characterized in that the photon chip be edge emitting or it is received swash
When light device, detector or modulator, then the structure further includes the wafer lining that photon chip transmitting or receiving end side is arranged in
Groove on bottom and for optical signal transmission.
5. structure according to claim 4, which is characterized in that the cavity and the groove use photoetching or etching technics
It processes and is formed in wafer-level photoelectric chip collaboration encapsulating structure.
6. -5 any structure according to claim 1, which is characterized in that the structure further includes the light being covered on wafer
Quick material, and by carrying out windowing wiring to light-sensitive material at electrical chip pad and photon chip pad and forming metal line
Layer.
7. a kind of photoelectric chip cooperates with packaging method characterized by comprising
On the wafer for be provided with photon chip and it is located at photon chip side setting cavity, and electrical chip is just being placed on to the chamber
In vivo；
Metal wiring layer of the setting for being connect respectively with electrical chip pad, photon chip pad on wafer；
Be arranged on the metal wiring layer for by the photon chip, electrical chip and the extraneous convex block being electrically attached or
Soldered ball；
It is cut to as at least one electrical chip and unit composed by least one photon chip, and forms wafer-level photoelectric
Chip cooperates with encapsulating structure.
8. the method according to the description of claim 7 is characterized in that the size of the cavity is opposite with the size of the electrical chip
It answers, so that the electrical chip pad is concordant with photon chip pad locations.
9. method according to claim 7 or 8, which is characterized in that the electrical chip uses conductive material and cavity bottom
Welding；
Alternatively, the cavity bottom is connected by the surface of deposited metal and wafer.
10. according to any method of claim 7-9, which is characterized in that the setting on wafer for respectively with
After the metal wiring layer that electrical chip pad, photon chip pad connect, the method also includes:
When the photon chip be edge emitting or received laser, detector or modulator when, then photon chip transmitting or
Setting is used for the groove of optical signal transmission in the wafer substrate of receiving end side；
Preferably, the cavity and the groove, which are cooperateed with using photoetching or etching technics in the wafer-level photoelectric chip, encapsulates knot
Processing is formed in structure.
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| CN112612748A (en) * | 2020-12-25 | 2021-04-06 | 南京蓝洋智能科技有限公司 | Super heterogeneous computing method based on extensible small chip architecture |
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Application publication date: 20190521 |