JPS58125824A - 金属シリサイド膜の形成方法 - Google Patents

金属シリサイド膜の形成方法

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Publication number
JPS58125824A
JPS58125824A JP57008712A JP871282A JPS58125824A JP S58125824 A JPS58125824 A JP S58125824A JP 57008712 A JP57008712 A JP 57008712A JP 871282 A JP871282 A JP 871282A JP S58125824 A JPS58125824 A JP S58125824A
Authority
JP
Japan
Prior art keywords
layer
film
carbon
gold
carbon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57008712A
Other languages
English (en)
Inventor
Yoshiya Ueda
上田 芳弥
Masaki Momotomi
百富 正樹
Fumie Okutsu
奥津 文江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57008712A priority Critical patent/JPS58125824A/ja
Priority to GB08300945A priority patent/GB2113913B/en
Priority to DE3301457A priority patent/DE3301457C2/de
Priority to US06/459,187 priority patent/US4581627A/en
Publication of JPS58125824A publication Critical patent/JPS58125824A/ja
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • H01L21/32053Deposition of metallic or metal-silicide layers of metal-silicide layers
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/083Ion implantation, general
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    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/14Schottky barrier contacts

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  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 発明の技術分野 この発明は絶縁膜又は半導体層の1鳩又は下層に金槁シ
リナイPMを形成する方法に関する。
発明の技術的背景 高速化、高密開化が要求される歳近の半導体装置(;お
いて、そのダート電極材料に種々工夫が加えられている
例えば、従来用いられている多結晶シリコン属に代わる
ものとして、タングステンW、モリブデンMo等の金−
膜、またはこれら金属とンリコ281の混合物からなる
金−Vり夛イド膜が用いられている。
背景技術の間騙点 しかしながら、こうした金属ノリサイド膜を例えば二酸
化ケイ素(840,)からなる絶縁膜上に形成し、その
後熱処理またはノナターニyダ(写真蝕刻)工程を通す
と、金−シリサイド真の剥がれを生じてしまうことがし
ばしば見られ番。
発明の目的 この発明は1記実情に鍍みてなされたもので。
その目的は、金属シリチイy膜と絶縁膜又は半導体層と
の密着性が向上し、金l1ilVす夛イPIEの剥がれ
を防止できる金−νり夛イド膜の形成方法を提供するこ
とにある。
発明の概要 この発明は1例えば下地絶縁編上に数10ムの薄い炭素
層を形成し、この炭素層上に金−Vり夛イド績を形成し
た俵、レーデ光線により1紀炭素層を加熱し、炭素を金
栖シリチイド膜及び下地絶縁膜内に拡散させるものであ
る。
発明の実施例 以下、図面を参照してこの発明の一実施例を説明する。
第1図はシリコン基板1の熱酸化にヨリ8ムOm1[J
を形成し、この8i0.lij上1ニー−中間層として
炭素層1を数10Hの厚さで形成した後、金鵬シリナイ
ド−例えばそすff7・vlJ夛イド(M・8轟寓)襖
4をスノ曽ツタリングにより形成した状態を示すIIT
面図である。
このようにしてシリコン基板1上に形成されたモリブデ
ン・V9ナイド膜4.炭素@a及び810、l[Jをレ
ーデ光線C二より加熱する。このレーデ光線の波長は、
前記三層構造中の炭素層Jに吸収端をもつものを選ぶ、
すなわち、モリブデン・シリ夛イ#P膜4の厚さ、及び
その組成比により適当に波長を選ぶものである。レーデ
光線で加熱後の状態を第2図に示す、同図において、レ
ーデ光線の加熱によりStO,膜Jkの炭素層1が、モ
リブデン・v I) fイド膜4及び8[)、1i!I
[2内に拡散されている。
この炭素層Jの拡散状態を、オーノエ電子分光分析(ム
E8)で確認した。その結果を#43図に示す、−3図
の縦軸は、三層構造を有する各種元素のオージェ信号強
度であり、横軸は各層の厚さを示している。ここで、そ
りゾーン・Vリチイド膜4.8ム0.膜2の領域でのM
o。
81.0の各元素のオージェ信号強度は示していないが
、ム領域がそりゾーン・シリ夛イド舗域、B領域が炭素
領域、C領域が8i0.領域である。また、図中実線は
レーデ光による加熱前の炭素信号を示し、破線は加熱後
の炭素信号強度を示し−ている。これにより、炭素層1
がレーデ光による加熱で、モリff”ン・Vリチイド膜
4及び840.gx内に拡散していることが確認された
この拡散した炭素+1i1 Jはモリブデン・νり夛イ
P属4.810□膜2間の接着強度を大きくしていると
考えられる。すなわち、そりブrン・Vリナイド膜*、
StO,膜2間の接着強度は、原子半径が小さく、かつ
モリブy”y−vす夛イW$4及び畠i0.編2の特性
を損うことのない例えば炭素層1からなる中間層を設け
、この中間層をモリ!デy−Vす夛イ#P膜4及びat
o。
膜2の双方に拡散させることで大きくなる。このように
して得られた癒すデデン4Vリナイドj1114は、そ
の後の半導体製造工程1例えば熱処理、酸処理工程を経
ても下地の8轟0置膜2とそリデデン・V9夛イド膜4
との間では剥がれを生じなかった・ さらに、モリブデン・シリナイP膜4の応力を測定した
。従来の840.yIi上に形成したモリブデン・V 
IJ ’!)イPIgは、熱処理艦=より凸方向に大キ
く反り、その時のモリブデン・Vダナイド碩自体の応力
は1.9 X 10  dye/龜 であった、これに
対し、この発明の方法により形成したモリプデy−v9
fイド膜4を1000℃、窒素中で30分間の熱処理し
た結果、凸方向の反りは少なく、また膜自体の応力も5
 X 10 dyw’sXと、従来の膜と比較して著し
い改良が見られた。
これは、そりf5’ン・シリ夛イド編4内に熱拡散した
炭素の効果と考えられる。
崗、上記実施例においては、金I11シリ夛イド膜はモ
リブデン・レリ夛イド礁4、下地絶縁膜は810m膜2
として説明したが、これに限定するものではなく、その
他の金属シリ夛イド編、絶縁属でもよいことは勿論であ
る。また、金輌しリチイド膜は、絶縁績の上層だけでな
く、下層に形成するようにしてもよく、さらに半導体層
の上層又は下層に形成するようにしてもよい。
発明の効果 以上のようにこの発明によれば、金調シリ夛イPl[ど
絶縁膜又は半導体層との密着性が向丘し、特に半導体装
置の製造に極めて有益である。
【図面の簡単な説明】
1111図はこの発明の一実施例に係る半導体装置の加
熱前の状態を示すth面図、鍋2図は上記装置の加熱後
の状態を示すth面図、第3図はL紀装置における炭素
層の拡散状態をオージェ電子昼光分析により示す図であ
る。 1・・・Vl!#コン轟板、1・・I轟0.膜、J・・
−責嵩層、4・・・そリブダン・Vリナイド属。

Claims (1)

    【特許請求の範囲】
  1. 絶縁膜又は半導体層のL層又は下層に金Ill!!/リ
    ナイド膜を形成する金属ノリサイド膜の形成方法におい
    て、前記金調v IJ夛イド−と前記絶縁膜又は半導体
    層との間に炭素からなる中間層を設け、この中間層を加
    熱し炭素を1紀金属νり夛イy膜内及び前記絶縁膜又は
    半導体層内に拡散させることを特徴とする金−Vリチイ
    VP膜の形成方法。
JP57008712A 1982-01-22 1982-01-22 金属シリサイド膜の形成方法 Pending JPS58125824A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57008712A JPS58125824A (ja) 1982-01-22 1982-01-22 金属シリサイド膜の形成方法
GB08300945A GB2113913B (en) 1982-01-22 1983-01-14 Semiconductor device and method for manufacturing the same
DE3301457A DE3301457C2 (de) 1982-01-22 1983-01-18 Halbleitervorrichtung und Verfahren zu ihrer Herstellung
US06/459,187 US4581627A (en) 1982-01-22 1983-01-19 Enhanced silicide adhesion to semiconductor and insulator surfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57008712A JPS58125824A (ja) 1982-01-22 1982-01-22 金属シリサイド膜の形成方法

Publications (1)

Publication Number Publication Date
JPS58125824A true JPS58125824A (ja) 1983-07-27

Family

ID=11700545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57008712A Pending JPS58125824A (ja) 1982-01-22 1982-01-22 金属シリサイド膜の形成方法

Country Status (4)

Country Link
US (1) US4581627A (ja)
JP (1) JPS58125824A (ja)
DE (1) DE3301457C2 (ja)
GB (1) GB2113913B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0296374A (ja) * 1988-10-03 1990-04-09 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

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Publication number Priority date Publication date Assignee Title
JPH0697693B2 (ja) * 1984-12-05 1994-11-30 株式会社東芝 Mos型fetのゲート構造の製造方法
US4737474A (en) * 1986-11-17 1988-04-12 Spectrum Cvd, Inc. Silicide to silicon bonding process
US4985371A (en) * 1988-12-09 1991-01-15 At&T Bell Laboratories Process for making integrated-circuit device metallization
US5254874A (en) * 1990-05-02 1993-10-19 Quality Semiconductor Inc. High density local interconnect in a semiconductor circuit using metal silicide
US5223456A (en) * 1990-05-02 1993-06-29 Quality Semiconductor Inc. High density local interconnect in an integrated circit using metal silicide
EP0720223B1 (en) * 1994-12-30 2003-03-26 STMicroelectronics S.r.l. Process for the production of a semiconductor device having better interface adhesion between dielectric layers
US5756391A (en) * 1995-03-24 1998-05-26 Kabushiki Kaisha Toshiba Anti-oxidation layer formation by carbon incorporation
JP2015170732A (ja) * 2014-03-07 2015-09-28 株式会社東芝 レーザ加熱処理方法、及び、固体撮像装置の製造方法
CN109234728B (zh) * 2018-10-18 2020-07-28 江苏理工学院 一种钼合金表面激光熔覆制备MoSi2涂层的方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4395813A (en) * 1980-10-22 1983-08-02 Hughes Aircraft Company Process for forming improved superconductor/semiconductor junction structures
US4404235A (en) * 1981-02-23 1983-09-13 Rca Corporation Method for improving adhesion of metal film on a dielectric surface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0296374A (ja) * 1988-10-03 1990-04-09 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

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Publication number Publication date
GB2113913A (en) 1983-08-10
DE3301457C2 (de) 1986-11-13
GB8300945D0 (en) 1983-02-16
GB2113913B (en) 1985-10-09
DE3301457A1 (de) 1983-08-04
US4581627A (en) 1986-04-08

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