JPS58117055A - スキヤン・デ−タ保護方式 - Google Patents

スキヤン・デ−タ保護方式

Info

Publication number
JPS58117055A
JPS58117055A JP56210685A JP21068581A JPS58117055A JP S58117055 A JPS58117055 A JP S58117055A JP 56210685 A JP56210685 A JP 56210685A JP 21068581 A JP21068581 A JP 21068581A JP S58117055 A JPS58117055 A JP S58117055A
Authority
JP
Japan
Prior art keywords
signal
scan
circuit
control section
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56210685A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0254582B2 (enExample
Inventor
Sumiko Sugihara
杉原　澄子
Toyoshi Yamada
山田　豊志
Koichi Aida
公一 会田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56210685A priority Critical patent/JPS58117055A/ja
Publication of JPS58117055A publication Critical patent/JPS58117055A/ja
Publication of JPH0254582B2 publication Critical patent/JPH0254582B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP56210685A 1981-12-30 1981-12-30 スキヤン・デ−タ保護方式 Granted JPS58117055A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56210685A JPS58117055A (ja) 1981-12-30 1981-12-30 スキヤン・デ−タ保護方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56210685A JPS58117055A (ja) 1981-12-30 1981-12-30 スキヤン・デ−タ保護方式

Publications (2)

Publication Number Publication Date
JPS58117055A true JPS58117055A (ja) 1983-07-12
JPH0254582B2 JPH0254582B2 (enExample) 1990-11-22

Family

ID=16593406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56210685A Granted JPS58117055A (ja) 1981-12-30 1981-12-30 スキヤン・デ−タ保護方式

Country Status (1)

Country Link
JP (1) JPS58117055A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495492B2 (en) 2006-09-12 2009-02-24 International Business Machines Corporation Dynamic latch state saving device and protocol
US7966589B2 (en) 2006-09-12 2011-06-21 International Business Machines Corporation Structure for dynamic latch state saving device and protocol

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7495492B2 (en) 2006-09-12 2009-02-24 International Business Machines Corporation Dynamic latch state saving device and protocol
US7966589B2 (en) 2006-09-12 2011-06-21 International Business Machines Corporation Structure for dynamic latch state saving device and protocol

Also Published As

Publication number Publication date
JPH0254582B2 (enExample) 1990-11-22

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