JPS58115572A - 起動制御方式 - Google Patents

起動制御方式

Info

Publication number
JPS58115572A
JPS58115572A JP21364181A JP21364181A JPS58115572A JP S58115572 A JPS58115572 A JP S58115572A JP 21364181 A JP21364181 A JP 21364181A JP 21364181 A JP21364181 A JP 21364181A JP S58115572 A JPS58115572 A JP S58115572A
Authority
JP
Japan
Prior art keywords
activation
address
specific address
slave
activated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21364181A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6326906B2 (cg-RX-API-DMAC7.html
Inventor
Masaaki Kobayashi
正明 小林
Noboru Yamamoto
昇 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21364181A priority Critical patent/JPS58115572A/ja
Publication of JPS58115572A publication Critical patent/JPS58115572A/ja
Publication of JPS6326906B2 publication Critical patent/JPS6326906B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP21364181A 1981-12-29 1981-12-29 起動制御方式 Granted JPS58115572A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21364181A JPS58115572A (ja) 1981-12-29 1981-12-29 起動制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21364181A JPS58115572A (ja) 1981-12-29 1981-12-29 起動制御方式

Publications (2)

Publication Number Publication Date
JPS58115572A true JPS58115572A (ja) 1983-07-09
JPS6326906B2 JPS6326906B2 (cg-RX-API-DMAC7.html) 1988-06-01

Family

ID=16642510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21364181A Granted JPS58115572A (ja) 1981-12-29 1981-12-29 起動制御方式

Country Status (1)

Country Link
JP (1) JPS58115572A (cg-RX-API-DMAC7.html)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5463644A (en) * 1977-10-31 1979-05-22 Toshiba Corp Multiprocessing system
JPS58101361A (ja) * 1981-12-14 1983-06-16 Hitachi Ltd デ−タ処理装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5463644A (en) * 1977-10-31 1979-05-22 Toshiba Corp Multiprocessing system
JPS58101361A (ja) * 1981-12-14 1983-06-16 Hitachi Ltd デ−タ処理装置

Also Published As

Publication number Publication date
JPS6326906B2 (cg-RX-API-DMAC7.html) 1988-06-01

Similar Documents

Publication Publication Date Title
TW469373B (en) System and method of preforming a memory transaction on a low pin count bus
EP0166272A2 (en) Processor bus access
US6115767A (en) Apparatus and method of partially transferring data through bus and bus master control device
JPS58115572A (ja) 起動制御方式
JPH0786865B2 (ja) 多重プロセッサ・レベル変更同期装置
JPS5854418A (ja) 割込み処理方式
JPH0426913Y2 (cg-RX-API-DMAC7.html)
JP2600376B2 (ja) メモリ制御装置
JP2817267B2 (ja) ブレークアドレス検出装置
JPS61250748A (ja) 情報処理装置のメモリアクセス方式
JPS6232832B2 (cg-RX-API-DMAC7.html)
JPH1011405A (ja) メモリアクセス競合制御システム
JP2968636B2 (ja) マイクロコンピュータ
JP2757034B2 (ja) マルチプロセッサシステムのデータチャネル装置起動方式とデータチャネル装置
JP2001043182A (ja) パラレルバスシステム
JPS588338A (ja) メモリ・システムにおけるバス制御回路
JPH05173936A (ja) データ転送処理装置
JPS5659339A (en) Input/output control unit
JPS59189433A (ja) ダイレクトメモリアクセスによるデ−タ消去方式
JP3236459B2 (ja) 共通バスのデータ転送における異常処理装置
JPH02249052A (ja) データ転送装置
JPS5851333U (ja) プログラム処理装置
JPH03182959A (ja) 高速コプロセサインタフェース機構
JPH06161903A (ja) メモリ内容複写制御方式
JPS63165940A (ja) デ−タ処理装置