JPS58101527A - Digital phase controlled oscillating circuit - Google Patents

Abstract

PURPOSE:To eliminate steady-state phase error, by controlling the frequency dividing ratio of a frequency divider with an output obtained from the output of a phase comparator multiplied with a coefficient. CONSTITUTION:An output signal (d) and a reference signal (i) are inputted to a comparator PD and an output deltan is generated and it is inputted to an integrator consisting of a multiplier MUL1, an integrator ADD1 and a latch LAT. An output Sn of the integrator is inputted to a multiplier MUL2. Outputs of the MUL1, MUL2 are summed. The result of addition is given to a variable frequency divider CTR to change the frequency dividing ratio. Taking the coefficient of MUL1, MUL2 at multiplication into consideration, the steady-state error can be eliminated.

Description

[Detailed Description of the Invention] (1) Technical field of oscillator The present IJI relates to a digital phase control oscillation circuit with a frequency gate and a lid, and is intended to specifically eliminate the steady phase difference between input and output signals. be.

(Technical Background 78) A digital phase-controlled oscillator circuit using an input signal (synchronized output signal 'Ik4I) using a PLL (PLL) has a phase input, an output signal, and a frequency input signal.

Figure 1111 is an example of a conventional frequency port, top-bottom digital position, and output path, where the OSC receives the input signal i (frequency f・')
A reference oscillator such as a crystal oscillator that oscillates at a fixed frequency N@f, which is double the fixed frequency, CTiL is a variable division ratio that divides its output N@f This is a phase comparator that compares the output phase of the CTR and the input phase, and a multiplier that multiplies the phase g*±JK coefficient kt obtained by the MULri compensator FD.

The center division ratio of the frequency divider CTR is N, which causes the g oscillator o
If the aco output N @ fl is frequency divided, the resulting output signal 40 frequency will be f.However, if a correction value of 10 kJ is given from the multiplier MUL, the frequency division ratio will be 1/(N±kJ)
9, the output iosm number * the input tox wave changes in the direction of the same wave f・゛ (in the direction of making Jt zero).

The second s is a maym chart that shows the control operation tm, and dn+m5=4. +kJ, ad, +k(i, -4,)
-----1■O relationship % ill
an, 'n is oscillation @oSc.

Set the N-divided clock generation time of the oscillator 08C as the reference time, and set the needle according to the number of clocks.
d, J value is 69, 'net e 'm+1 @
'1141 is the value at the next reference time. Here l, d
, J is a time series that changes every N clock periods T· of the oscillator 08C, then by 2 conversion, the 0 equation can be expressed as the equations ■ and ■.

However, it is assumed that I, D, and j are respectively t, d, and J72 transformed, and z;・i・''*T@−1/f・.

(Conventional technology and problems) By the way, if there is a frequency deviation between the reference oscillator O8C and the input i in the above-mentioned digital phase controlled oscillator circuit, a steady phase error that cannot be removed will occur in the input/output signal amount. For example, the input 1 If it is assumed that T changes by ε (constant), then I can be expressed as shown below.

Also, according to the final value theorem, the final (steady) value of J is 0.

Therefore, a steady phase error consisting of equations 0 to 0 occurs. In the 110th circuit configuration, K to reduce this steady-state phase error KAt must also be satisfied for the high stability of the reference oscillator osci, but this becomes a factor in cost savings.

(4) Object of the Invention The present invention attempts to eliminate the above-mentioned steady phase error by adding a simple circuit without particularly increasing the frequency stability ft of the reference oscillator.

(5) Configuration of the invention The uninvented digital phase control oscillator circuit includes a reference oscillator,
A frequency divider of the Bunkahicho variant which divides the frequency of the output and generates an output signal, a comparator that compares the phases of the cough output signal and the input signal, and a phase difference obtained by the comparator. A first multiplier that multiplies the phase difference, an integrator that integrates the limb phase difference, a 112 multiplier that multiplies the output of the integrator by a coefficient, and the outputs of the first and second multipliers are added together. The present invention is characterized by comprising an adder that changes the frequency division ratio of the frequency divider by 9 using the added value.

(6) Embodiments of the Invention The present invention will now be described in detail with reference to the illustrated embodiments. tssrIXAFi An embodiment of the present invention
And what's inside the broken line! [Added to 1@ is the next circuit. IN in the diagram
T is an integrator that integrates the output J of the comparator 1'D by one time, and in this example, it is composed of an adder DDI and a latch circuit LMT. S.I.
I is an integral output, which is the sum of the current phase difference J and T, and the integral output 8*1 up to #1 held in the circuit LAT. This integral output BmK company j1g20
It is multiplied by a coefficient kl in a multiplier MULs. DDn is an adder that adds the outputs ksJ, , ksB of the first and lE2 multipliers MULI, MULm, and its output kIJm+klBm is given to the coulter CTRjC. The multiplier MUL in Figure 1 is the multiplication @ MUL in Figure 1.
This is the same as , and the phase difference Jn is multiplied by a coefficient of 1.

According to the configuration of this example, 464＠m櫨! l + kl Jm + kg
gn
・・−−・・−−１ ■JBe=i, -d,
'”°°゛°°°°■8rh z
Jm + 8m-t ・=-〇 holds true. Therefore, from these equations, the following z-transformed equation can be obtained.

If you use this 0 formula and the 0.0 formula above, you will get L fish! 11 Jn = 0
・・・・・・－・＠■■O■ is derived. According to the circuit configuration shown in Figure JI5, this is true regardless of the stability of the reference oscillation @OBC. This means that the steady phase error between d converges to zero.

(7) Effect of invention According to the present invention as described above, the frequency port.

The 110 digital phase controlled oscillator circuit has the advantage of completely eliminating the steady phase error between the input and output signals with a simple additional circuit that improves the stability of the reference oscillator.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional digital phase controlled oscillator, Figure 2 is a time chart for explaining its operation, and Figure 5 is a circuit diagram showing an example of a conventional digital phase control oscillator.
flA is a circuit diagram showing one embodiment of the present invention. In the figure, OSC is a reference oscillator, c'ri is a frequency divider, and PDr
! The phase comparator, MULI, MUL multiplier, INT integrator, and MUDDm are adders. Applicant Fujitsu Limited

Claims (1)

[Claims] A reference oscillator, a variable division ratio O frequency divider that divides its output to obtain an output signal, and a wrinkle output signal and an input signal O position 11t.
- a comparator for comparison, a III multiplier for multiplying the phase difference obtained by the comparator by a coefficient, an integrator for integrating the wrinkle phase me, and a 20th multiplier for multiplying the output of the integrator by a coefficient; 1
A digital phase control oscillation circuit comprising: an adder that adds the respective outputs of wl11 and the second multiplier and varies the frequency division ratio of the frequency divider O using the added value.