JPH02143785A - Phase comparator circuit and phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain an output in response to a phase error even if the error is large by adding an output of an averaging circuit and an output of a slicer circuit. CONSTITUTION:A latch circuit 5 latches an output of a counter circuit at the edge of a horizontal synchronizing signal. When the output of the latch circuit 5 is inputted to a slicer circuit 4 having a characteristic whose output is zero when a small input is given. The output of the slicer circuit 4 and the output of the averaging circuit 1 are added by an adder circuit 2 to obtain a phase comparison characteristic proportional to the phase difference. Thus, even when the phase error is large, an output proportional to the phase error is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase synchronization circuit and a phase comparison circuit for generating a clock synchronized with a reference signal in video signal processing of televisions, video tape recorders, etc. .

BACKGROUND OF THE INVENTION In recent years, there has been an increasing demand for digital processing of video signals, and as a means for generating the necessary clocks, a phase synchronization circuit that generates a clock synchronized with a reference signal such as a horizontal synchronization signal is often used. A conventional phase comparison circuit for comparing the phases of a reference signal and a clock used in such a phase locked circuit will be described below with reference to the drawings. FIG. 4 is a block diagram showing the configuration of a conventional phase comparator circuit, and FIG. 5 is a waveform diagram showing waveforms of various parts of the conventional example of FIG. The horizontal synchronizing signal is A/D converted by an A/D converter 23 and input to an averaging circuit 20 . Further, the clock of the A/D converter 23 is counted by the counter circuit 22, and in response to the output thereof, the control circuit 21 averages the A/D converted horizontal synchronizing signal for a period in which the output of the counter circuit 22 takes a constant value. The averaging circuit 20 is controlled as follows.

This operation will be explained using FIG. 5.

FIG. 5(a) shows the output waveform of the counter circuit 22, and the output increases each time a clock is input, and is reset when the dynamic range of the counter is exceeded. Further, (b) shows the waveform of the horizontal synchronizing signal input to the averaging circuit 20. The circles indicate sampling points near the edge, and the rest are omitted. For example, the output of the counter circuit 22 is expressed as a positive and negative value like a two's complement number, and when the output of the counter circuit 22 takes a value from -1 to 1, the control circuit 21 averages the horizontal synchronizing signal. If the circuit 20 is controlled, (
The data of the three points indicated by the circles in b) are averaged. If the phase of the horizontal synchronization signal has now advanced with respect to the counter output, the sampling point at which the horizontal synchronization signal is averaged is (b)
, the average value increases as it moves to the left. If you are late, it will decrease. Therefore, the output of the averaging circuit 20 exhibits a value as shown in (C) with respect to the phase difference between the counter output and the horizontal synchronizing signal, and operates as a phase comparison circuit. Such an example is ``Nice Teeny Electronica J 27, 1-2,
1985PIOIN107.

Problems to be Solved by the Invention However, as can be seen from FIG. 5(C), the above configuration has the disadvantage that the output does not change when the phase error exceeds a certain value. had the disadvantage of poor response when the phase error was large.

In view of this, an object of the present invention is to provide a phase comparator circuit and a phase synchronization circuit that have good response even when a phase error is large.

Means for Solving the Problems In order to solve the above problems, the phase comparison circuit of the present invention includes an A/D converter that digitizes a horizontal synchronizing signal, a counter circuit that counts clocks, and an output value of the counter circuit. an averaging circuit that averages the digitized horizontal synchronization signal for a period within a preset range; a latch circuit that latches the output of the counter circuit at the edge of the horizontal synchronization signal; The configuration includes a slicer circuit that makes the output zero when , and an adder that adds the output of the averaging circuit and the output of the slicer circuit.

Effect of the Invention With the above-described configuration, the present invention can obtain an output corresponding to a large phase error even when the phase error is large. Further, according to the present invention, by using this phase comparator circuit, it is possible to configure a phase synchronization circuit that has good response even when the phase error is large.

Embodiments Hereinafter, a phase comparator circuit of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the phase comparator circuit of the present invention, and FIG. 2 is a waveform diagram showing waveforms of various parts of the embodiment shown in FIG.

In Figure 1, A/D converter 9, averaging circuit 1, control circuit 3
, the counter circuit 6 is the conventional example A shown in FIG.
It operates in the same way as the /D converter 23, the averaging circuit 20, the control circuit 21, and the counter circuit 22. Therefore, the output of the averaging circuit 1 exhibits the characteristics shown in FIG. 2(C) as in the conventional example. Figure 2 (a
) shows the output waveform of the counter circuit 6, and (b) shows the horizontal synchronizing signal waveform input to the averaging circuit 1. The latch circuit 5 latches the output of the counter circuit 6 at the edge of the horizontal synchronization signal. In this example, it is assumed that the negative edge is used to latch. When the phase of the horizontal synchronizing signal (b) advances with respect to the phase of the output (a) of the counter circuit 6, the latch circuit 5 latches the large value of the counter circuit 6, so its output increases, and decreases when delayed. Therefore, the output of the latch circuit 5 for the phase difference is (
d). The slicer circuit 4 has a characteristic that the output of the latch circuit 5 becomes zero when the input is small.
(f) shows the characteristics of the output when input to By adding the output of the slicer circuit 4 and the output of the averaging circuit 1 in the adder circuit 2, it is possible to obtain a phase comparison characteristic proportional to the phase difference, as shown in (g).

In the above explanation, the horizontal synchronization signal shown in Fig. 2(b) was used as an example of the reference signal, but if the duty ratio is small, there is no problem if the waveform is shaped, and the input signal is the horizontal synchronization signal. It is not limited to.

Next, an embodiment of a phase synchronization circuit using the phase comparison circuit of the present invention will be described with reference to FIG. The phase comparator circuit 8 in FIG. 3 is the same as the previously described embodiment of the phase comparator circuit in FIG. 1, and the same elements are given the same numbers.

The horizontal synchronizing signal A/D converted by the A/D converter 10 is input to the averaging circuit 1 of the phase comparison circuit 8, and the clock supplied to the A/D converter 10 is also input to the counter circuit 6. . Since the phase comparator circuit 8 operates as described above, its output is proportional to the phase difference between the counter circuit 6 and the A/D converted horizontal synchronizing signal. This output is filtered by a low-pass filter 11 and added to an adder 13.14.
and D flip-flop (D-FF) 15 and ROM (
Read ONLY Memory) l Controls the frequency of the variable frequency oscillator 12 composed of 9. In the variable frequency oscillator 12, an adder 13 adds a value fc corresponding to the center frequency to the input signal, and the output thereof is accumulated using an adder 14 and a D flip-flop 15.

The clock of the D flip-flop 15 is the clock generator 1.
Give from 8. For example, a crystal oscillator is used as the clock generator 18. Since the adder 14 overflows when the dynamic range is exceeded, a silver wave having a frequency proportional to the input is obtained at its output. If this silver wave is input to the address of the ROM 19 in which sine wave data has been written in advance, a sine wave will be obtained as the output. This signal is converted into an analog signal by a D/A converter 16 and harmonics are extracted by a band pass filter 17 to obtain an analog oscillation output. If this output is used as a clock and is fed back to the A/D converter 10 and the counter circuit 6, the output of the counter circuit 6 and the phase of the horizontal synchronization signal will be synchronized. When the frequency ratio is n, the frequency is n times that of the horizontal synchronizing signal. Using this configuration, a phase synchronization circuit for obtaining a clock that is an arbitrary multiple of the horizontal synchronization signal can be realized using a digital circuit.

Furthermore, in this embodiment, the signal obtained as the output of the bandpass filter 17 is a signal obtained by D/A converting the output of the variable frequency oscillator 12 configured with a digital circuit, so the frequency is determined by the sampling theorem to operate the variable frequency oscillator 12. The output frequency of the clock generator 18 must be one-half or less. Therefore, when oscillating a frequency higher than that, a multiplier circuit 20 for multiplying the output of the bandpass filter 17 may be provided after the bandpass filter 17.

Note that if the output of the variable frequency oscillator 12 is a silver wave, R
OM19 is not required.

Effects of the Invention As described above, the phase comparator circuit of the present invention can obtain an output proportional to the phase error even when the phase error is large.

Moreover, by using the phase comparator circuit of the first invention, the phase synchronization circuit of the present invention can obtain good response characteristics even when the phase error is large. Further, the phase synchronized circuit of the present invention can generate a clock for A/D converting the reference signal from the A/D converted reference signal using a digital circuit.

Moreover, by using a multiplier circuit, the phase synchronized circuit of the present invention can increase the frequency of the generated clock to more than half the frequency of the clock that operates the variable frequency oscillator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a waveform diagram and characteristic diagram showing waveforms of each part of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the first embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a conventional example, and FIG. 5 is a waveform diagram and characteristic diagram showing waveforms of various parts of the conventional example. 1... Average circuit, 2... Addition circuit, 3...
・Control circuit, 4... Slicer circuit, 5...
Latch circuit, 6... Counter circuit, 8... Phase comparison circuit, 9°10... A/D converter, 11...
・Low pass filter, 12... variable frequency oscillator,
18... Clock generator, 20... Multiplier circuit. Name of agent: Patent attorney Shigetaka Awano and 18 others

Claims (4)

[Claims] (1) An A/D converter that digitizes the horizontal sync signal, a counter circuit that counts clocks, and an average of the digitized horizontal sync signal for a period when the output value of the counter circuit is within a preset range. a latch circuit that latches the output of the counter circuit at the edge of the horizontal synchronization signal, a slicer circuit that makes the output zero when the output of the latch circuit is within a certain range, and the average circuit A phase comparison circuit comprising an adder for adding an output and an output of the slicer circuit. (2) A phase comparison circuit according to claim 1, a low-pass filter that filters the output of the phase comparison circuit, a variable frequency oscillator that oscillates at a frequency proportional to the output of the low-pass filter, and an output of the variable frequency oscillator that filters the output of the variable frequency oscillator. The device includes a D/A converter that performs D/A conversion, and a bandpass filter that filters the output of the D/A converter, and the output of the bandpass filter is used as the clock of the A/D converter, and the phase A phase synchronization circuit, wherein the comparison circuit compares the phase of the clock and the digitized horizontal synchronization signal. (3) The variable frequency oscillator includes an adder circuit that adds data from one clock ago to the input data, and an adder circuit that adds the output of the adder circuit to the input data.
3. The phase synchronization circuit according to claim 2, further comprising a D flip-flop that delays the clock and feeds back to the adder circuit. (4) The phase synchronized circuit according to claim 2, further comprising a multiplier circuit that multiplies the output of the bandpass filter, the output of which is used as a clock for the A/D converter.