JP2508443B2 - Clock synchronization circuit for sampling rate conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving Problems (FIG. 1) F Action G Example G ₁ Sampling rate conversion circuit (No. ₁ ) Fig. 5) G ₂ clock synchronization circuit (I) (Fig. 1) G ₃ clock synchronization circuit (II) (Fig. 2) H Effect of the invention A Industrial field of application The present invention relates to clock synchronization of a sampling rate conversion circuit. Regarding the circuit.

B Outline of the Invention The present invention relates to a clock synchronization circuit of a sampling rate conversion circuit for converting a first digital video signal having a first sampling frequency into a second digital video signal having a second sampling frequency. , A circuit for supplying a synchronization signal of the first digital video signal to generate first and second clock signals having frequencies equal to the first and second sampling frequencies, respectively. First and second variable oscillators each having an oscillation frequency equal to the frequency are provided, and the signal related to the oscillation output of the first variable oscillator and the synchronization signal of the first digital video signal are phased by the first phase comparator. The second phase comparator compares the two signals respectively related to the oscillation outputs of the first and second variable oscillators, and the first phase comparator compares the two signals. Controlling the oscillation frequency of the first variable oscillator and controlling the oscillation frequency of the second variable oscillator by the comparison output of the second phase comparator. From the first and second respectively
By obtaining the clock signal of, the first and second clock signals with high frequency accuracy can be obtained.

C Conventional Technology As a digital VTR, there is a component type digital VTR called a 4: 2: 2 type digital VTR. In this component type digital VTR, the digital luminance signal is sampled at a sampling frequency of 13.5 MHz, and the digital red and blue difference signals are sampled at a sampling frequency of 6.75 MHz, respectively.

On the other hand, there is a composite digital VTR. In this composite type digital VTR, the composite color video signal is 4f _SC (where f _SC represents the color subcarrier frequency, and in the case of the NTSC system, 4f _SC = 14.3181).
Sampling frequency of 8MHz).

Between digital VTRs that record and reproduce digital video signals having different sampling frequencies, it is necessary to convert the sampling frequency (sampling rate) of the digital video signal of one sampling frequency into the digital video signal of the other sampling frequency. There may be.

D Problem to be Solved by the Invention In view of the above problems, the present invention provides sampling for converting a first digital video signal having a first sampling frequency into a second digital video signal having a second sampling frequency. In a clock synchronization circuit of a rate conversion circuit, which supplies a synchronization signal of a first digital video signal to generate a first clock signal and a second clock signal having a first sampling frequency and a second sampling frequency, respectively, It is intended to propose a device that can obtain the first and second clock signals with high frequency accuracy.

E Means for Solving Problems The present invention, as shown in FIG. 1, converts a first digital video signal having a first sampling frequency into a second digital video signal having a second sampling frequency. Sampling rate conversion circuit clock synchronization circuit (2
0), the circuit for supplying the synchronization signal of the first digital video signal to generate the first and second clock signals equal to the first and second sampling frequencies, respectively. A first variable oscillator (5) having an oscillation frequency equal to, and a second variable oscillator (1) having an oscillation frequency equal to the second sampling frequency.
2) and a first phase comparator (3) or (1) to which a signal related to the oscillation output of the first variable oscillator (5) and a synchronization signal of the first digital video signal are supplied and compared. , A second phase in which both oscillation outputs of the first and second variable oscillators (5) and (12) are respectively supplied via the first and second signal supply circuits K ₁ and K ₂ for comparison. Having a comparator (10),
The oscillation frequency of the first variable oscillator (5) is controlled by the comparison output of the first phase comparator (3) or (1), and the second phase comparator (10) compares the oscillation frequency. It is arranged such that the oscillation frequency of the second variable oscillator (12) is controlled and the first and second clock signals are obtained from the first and second variable oscillators (5) and (12), respectively. is there.

According to the present invention, the signal related to the oscillation output of the first variable oscillator (5) and the synchronizing signal of the first digital video signal are supplied to the first phase comparator (3) or (1). And compare the phases. First and second variable oscillators (5), (1
2) Both oscillation outputs are respectively fed to the first and second signal supply circuits.
It is supplied to the second phase comparator (10) via K ₁ and K ₂ for phase comparison. The oscillation frequency of the first variable oscillator (5) is controlled by the comparison output of the first phase comparator (3) or (1). The oscillation frequency of the second variable oscillator (12) is controlled by the comparison output of the second phase comparator (10). Then, the first and second variable oscillators (5) and (12) respectively obtain the first and second clock signals.

G Embodiment G ₁ Sampling rate conversion circuit First, an example of a sampling rate conversion circuit to which the present invention is applied will be described with reference to FIG. T ₅ is
An input terminal to which a first digital luminance signal having a first sampling frequency (a signal separated from a composite digital color video signal) is supplied, T ₆ is a second digital luminance signal having a second sampling frequency. It is the resulting output terminal. Here, the first sampling frequency of the first digital luminance signal is 4f _SC = 14.31818 MHz, and the second sampling frequency of the second digital luminance signal is 1
This is the case when it becomes 3.5 MHz.

The first and second sampling frequencies 1
The ratio of 4.31818MHz and 13.5MHz is 35:33, which is a simple integer ratio.

Reference numeral (18) is a digital filter, which is a circuit for increasing the first sampling frequency of the first digital luminance signal input to the input terminal T ₅ by 33 times. Reference numeral (20) is a clock synchronization circuit, and its input terminals T ₁ and T ₂ have a horizontal synchronization signal HD of the first digital luminance signal supplied to the input terminal T ₅ and a component digital to which the first digital luminance signal belongs. A burst signal BT (also a kind of synchronization signal) in the color video signal is supplied, and its output terminals T ₃ and T _{4 have} first and second sampling frequencies respectively equal to the first and second sampling frequencies. Clock signals CLK ₁ and CLK ₂ are obtained.

Reference numeral (21) is a latch circuit (comprising a D-type flip-flop circuit), which is supplied with the output of the digital filter (18) and is supplied with the second clock signal CLK ₂ from the output terminal T ₄ of the clock synchronization circuit (20). Latched.

The first clock signal CLK ₁ from the clock synchronization circuit (20) is supplied to each part of the digital filter (18).

Next, prior to the description of the digital filter (18) of FIG. 5, its basic principle will be described with reference to FIG. The digital filter of FIG. 6 is a circuit equivalent to the digital filter (18) of FIG. (18'D) indicates a delay circuit, which is a delay element having a delay time equal to the sampling period T'corresponding to a sampling frequency of 4f _SC (MHz) x 33, and the order of the filter (for example, 60).
0x700 degree) x 33 units are connected in cascade. (1
8'M) represents a coefficient multiplying circuit, which signals the output side of the delay elements of the connection point and the final stage of each delay element are respectively supplied at the input terminal T _5, the delay circuit (18'D) It is composed of filter order × 33 + 1 coefficient multipliers, and each coefficient is A ′ ₁ , A ′ ₂ , ..., A′n, A′n + ₁ , A′n + ₂ ,.
+ _3, and A'nmax. These delay elements are divided into n (here, 33) pieces starting from the third delay element from the input terminal T ₅ side. When Thus, at some point, coefficients A _'3,
A'n + ₃ . If the digital signal is supplied to the coefficient multipliers for every n stages of ..., The digital signal is not supplied to the remaining n-1 coefficient multipliers at that time.
Therefore, n (= 33) delay elements are grouped together with a delay amount of T ', and the delay amount is T (= nT') as shown in FIG. 5, that is, equal to the sampling period corresponding to the sampling frequency of 4f _SC. It can be replaced with a delay element. Therefore, the delay circuit (18) of the digital filter (18) in FIG.
D) is a circuit in which such delay elements whose delay amount is T are cascade-connected by the order of the filter (this is k + 1).

In the digital filter (18) of FIG. 5, the coefficients of the k + 2 coefficient multipliers that form the coefficient multiplication circuit (18M) are
Corresponding to the coefficient of each coefficient multiplier of the coefficient multiplier circuit (18'M) of FIG. 6, there are 35 variations in each sampling period T. Therefore, the digital filter (18) of FIG. 5 is provided with a coefficient generating circuit (19) for generating data of such changing coefficients A ₀ , A ₁ , A _2, ..., Ak, and a clock synchronizing circuit (20 ) From the first clock signal CLK ₁ . or,
Although not shown, the first clock signal CLK ₁ is also supplied to the delay circuit (18D).

5 and 6, (18S), (18'S)
Is an adder circuit for adding the respective outputs of the coefficient multipliers (18M) and (18'M) respectively.

This digital filter (18) exhibits a low-pass characteristic having a cutoff frequency of 4f _SC / 2 = 2f _SC, as shown by the solid line in FIG. The broken line in FIG. 7 shows the frequency spectrum of the signal when the filter characteristic is ignored.

Then, the digital filter (18) samples the first digital luminance signal supplied to the input terminal T ₅ by the interpolation based on this low-pass filter characteristic at the sampling frequency 33 times the first sampling frequency. It is converted into the digital luminance signal. That is, even if the input digital signal of the coefficient multiplier constituting the coefficient multiplying circuit (18'M) described in FIG. 6 is 0, it is equivalent to the fact that the input digital signal of a certain level is supplied by the interpolation processing. Becomes

Then, the digital luminance signal sampled at the sampling frequency 33 times the first sampling frequency from the digital filter (18) is supplied to the latch circuit (21), and the digital luminance signal from the clock synchronization circuit (20) By latching with the second clock signal having the sampling frequency of 2, that is, 13.5 MHz, the second digital luminance signal having the second sampling frequency is output to the output terminal T ₆ .

In the sampling rate conversion circuit of FIG. ₅ , the first sampling frequency of the first digital luminance signal input to the input terminal T ₅ is the same as that of the second digital luminance signal output to the output terminal T ₆ . Although the case where the sampling frequency is higher than 2 has been described, in the opposite case, a pair of the digital filters of FIG. ₅ are provided in parallel with the input terminal T ₅ (however, the coefficients are different from each other), and each output thereof is It is received by another latch circuit, and each latch output is switched by the changeover switch to be supplied to the latch circuit (21).

G ₂ Clock Synchronization Circuit (I) Next, with reference to FIG. 1, an example of the clock synchronization circuit of the sampling rate conversion circuit of FIG. 5 described above, that is, one embodiment of the present invention will be described. In Figure 1, (14) is
First clock signal [the frequency is 4f _SC (= 14.31818M
Hz)], and (15) is a PLL circuit that generates a second clock signal (its frequency is 13.5 MHz).

First, the first PLL circuit (14) will be described.
(5) is a first voltage-controlled oscillator (variable oscillator), which is controlled so that its oscillation frequency is 4f _SC . The oscillation output of the oscillator (5) is output to the output terminal T ₃ as the first clock signal. The oscillation output of the oscillator (5) is supplied to a frequency divider (6) having a frequency division ratio of 1/4 and is frequency-divided, and then the frequency of the signal f _SC from the frequency divider (6) is phase-compared. The signal is supplied to the device (1) and is phase-compared with the burst signal (the burst signal of the composite digital color video signal to which the first digital luminance signal belongs) BT (the signal whose frequency is f _SC ) from the input terminal T ₁ . The phase comparison output from the phase comparator (1) is supplied to the voltage controlled oscillator (5) as a frequency control signal through the low pass filter (2) and further through the fixed contact b and the movable contact a of the changeover switch SW _1. It

Further, the oscillation output of the oscillator (5) is supplied to a cascade circuit of a frequency divider (7) having a frequency division ratio of 1/35 and a frequency divider (8) having a frequency division ratio of 1/26, respectively. The frequency obtained from this is 4f _SC ÷ 910 = the signal of horizontal frequency is supplied to the phase comparator (3) and the horizontal synchronizing signal from the input terminal T ₂ (horizontal synchronizing signal belonging to the first digital luminance signal Signal) HD and phase compared. The phase comparison output from the phase comparator (3) is supplied to the voltage controlled oscillator (5) as a frequency control signal through the low pass filter (4) and further through the fixed contact c and the movable contact a of the changeover switch SW _1. It It should be noted that the changeover switch SW ₁ may select any changeover state.

Further, the horizontal synchronizing signal HD from the input terminal T ₂ is supplied to the differentiating circuit (9) and differentiated, and the differentiated output is divided by the fixed contact c and the movable contact a of the changeover switch SW ₂ as a lock circuit. Divider (counter) with a ratio of 1/35
It is supplied to the reset terminal of (7). The frequency divider (7) is reset when a voltage of 0 V is supplied to the reset terminal. Also, changeover switch
The voltage VE (= + 5V) is supplied to the other fixed contact b of SW ₂ , and when this is supplied to the reset terminal of the frequency divider (7), this frequency divider (7) outputs its own carry signal. Is reset with.

Next, the second PLL circuit (15) will be described. (12)
Is a second voltage controlled oscillator with an oscillation frequency of 13.5MHz
Is controlled to become. The oscillation output of the oscillator (12) is output to the output terminal T ₄ as the second clock signal. The oscillation output of the oscillator (12) is supplied to the frequency divider (13) having a frequency division ratio of 1/35 through the _second signal supply circuit (K ₂ ), and is then frequency-divided. A signal with a frequency of 13.5 MHz ÷ 33 from (13) is supplied to the phase comparator (10). Further, the oscillation output of the oscillator (5) is the first signal supply circuit.
A signal having a frequency of 4f _SC MHz ÷ 35 is supplied to the phase comparator (10) through K ₁ , that is, through the frequency divider (7) having a division ratio of 1/35, and the frequency divider is supplied. The phase is compared with the signal from (13) (13.5 MHz / 33 signal). Since the ratio of the first sampling frequency 4f _SC (= 14.31818MHz) and the second sampling frequency 13.5MHz is 35:33 as described above, 4f _SC MHz which is phase-compared by the phase comparator (10).
The frequency of ÷ 35 and the frequency of 13.5MHz ÷ 33 are equal. The comparison output of the phase comparator (10) is supplied to the voltage controlled oscillator (12) as an oscillation frequency control signal through the low pass filter (11).

Next, the operation of this clock synchronization circuit will be described with reference to the waveform diagram of FIG. 3 and the conversion noise explanatory diagram of FIG. First
The first and second clock frequencies of the second and second clock signals are, respectively, 4f _SC = 4 × 3.58 MHz = 14.318 as described above.
It is 18MHz and 13.5MHz, and the number of samples in one line of the luminance signal is 910 (= 35 × 2 when 4f _SC = 14.318 18MHz).
6) In case of 13.5MHz, it becomes 858 (= 33 × 26), and the ratio is 3
It is 5:33. Considering the first and second sampling frequencies of the first and second digital luminance signals, 14.31818MHz and 13.5MHz, as shown in FIGS. 3B and 3C, sample points where the phases are synchronized every 35 and 33 samples. a _1b , a _1c , ...; a _2b , a
There are 26 places of _2c , ... in one line.

The horizontal synchronizing signal HD from the input terminal T ₂ is supplied to the changeover switch SW ₂ via the differentiating circuit (9), but if the movable contact a is changed over to the fixed contact c side, the frequency divider (7) changes The value of the time l from the leading edge of the horizontal synchronizing signal shown in FIG. 3A to the sample point a _1b can be made constant by being reset by the horizontal synchronizing signal HD. If the movable contact a of the changeover switch SW ₂ is switched to the fixed contact b side, the frequency divider (7)
Since the voltage VE is supplied from the voltage source to the reset terminal of, and the frequency divider (7) is not reset by an external signal, the value of l shown in FIG. 3A is not a constant value. The timings of the sample points a _1b and a _1c shown in FIGS. 3B and 3C with respect to the horizontal synchronizing signal HD are indefinite.

The first and second clock signals from the output terminals T ₃ and T ₄ in FIG. 1 are supplied to the digital filter (18) and the latch circuit (21) in FIG. 5, respectively.

Now, in the sampling rate conversion circuit of FIG. 5, since a high-order filter of the order of 600 to 700 is used as the digital filter (18) as described above, the number of effective bits weighted to this filter is a hardware factor at the time of design. 4B, the conversion noise TN ₁ as shown in FIG. 4B is generated. Looking at such conversion noise on the screen (16) in Fig. 4A,
Sampling frequency 4f _SC (= 14.31818MHz) and 13.5MHz
At the 26 sample points a ₁ , a ₂ …… a ₂₆ where the phase of s is synchronized, vertical stripes (15a), (15a) …… appear at a fixed position. This conversion noise is not so noticeable in one conversion of the sampling rate, but in the case of repeating dubbing or editing, the conversion of the sampling rate is performed several times. In this case, the conversion noise TN ₁ is 26 times sample points a ₁ , a ₂ ... A like the conversion noise TN ₂ shown by the broken line in FIG. 4B.
There is a problem that it increases on ₂₆ and vertical stripes (15a) stand out.

Therefore, in the clock synchronization circuit of FIG. 1, if the changeover switch SW ₁ is switched so that the frequency dividing circuit (7) is not reset by the horizontal synchronization signal HD, the value of 1 in FIG. 3A becomes undefined. Sample points a ₁ , a ₂ , a ₃ …… a on the video signal
The positions of ₂₆ will vary, that is, for example, 26 sampling points a ₁ , a ₂ at the time of the first sampling rate conversion.
If conversion noise TN _1a appears at the position indicated by a ₂₆ as shown in FIG.
The sampling point of the fourth time is the fourth point at the position shown by b ₁ , b ₂ , b ₃ ... b ₂₆ .
The converted noise TN _1b appears as shown in FIG. C, the positions of the vertical axes (15a) and (15b) on the image are random, and the noise is less noticeable. On the other hand, if the movable contact a of the changeover switch SW ₂ is switched to the fixed contact c side, the frequency divider (7) is reset by the horizontal synchronizing signal HD, and the sampling points a _1b , a _{2b of} the first digital luminance signal. ,, and the sampling points a _1c , a _2c , ... Of the second digital luminance signal become in phase with each other every 26 points, and adjustment of each digital VTR and the like becomes convenient.

G ₃ Clock Synchronizing Circuit Next, another example of the clock synchronizing circuit, that is, another embodiment of the present invention will be described with reference to FIG. In FIG. 2, (14a) is the first clock signal (whose frequency is 13.
The first PLL circuit for generating 5 MHz), and (15a) is the PLL circuit for generating the second clock signal [the frequency of which is 4 f _SC (= 14.31818 MHz)].

First, the first PLL circuit (14a) will be described. (Five
a) is a voltage-controlled oscillator, whose oscillation frequency is controlled to be 13.5MHz. The oscillation output of the oscillator (5a) is output to the output terminal T ₃ as a first clock signal. The oscillation output of the oscillator (5a) is supplied to a cascade circuit of a frequency divider (7a) with a division ratio of 1/33 and a frequency divider (8a) with a division ratio of 1/26, and the frequency is divided. The obtained frequency is 13.5MHz
÷ 858 = A signal of horizontal frequency is supplied to the phase comparator (3a) and the phase is compared with the horizontal sync signal [horizontal sync signal belonging to the first digital luminance signal (digital component signal)] HD from the input terminal T _2. To be done. This phase comparator (3a)
The phase comparison output from is supplied to the voltage controlled oscillator (5a) as a frequency control signal through the low pass filter (4a).

Also, the horizontal synchronizing signal HD from the input terminal T ₂ is
It is supplied to a) and differentiated, and the differentiated output is a frequency divider (counter) (7a) with a frequency division ratio of 1/33 as a lock circuit through the fixed contact c and the movable contact a of the changeover switch SW _2.
It is supplied to the reset terminal of. In addition, this reset terminal
When a voltage of 0V is supplied, this frequency divider (7a) is reset. Further, the voltage VE (+ 5V) is supplied to the other fixed contact b of the changeover switch SW ₂ , and when this is supplied to the reset terminal of the frequency divider (7a),
This frequency divider (7a) is reset by its own carry signal.

Next, the second PLL circuit (15a) will be described. (12
a) is a voltage-controlled oscillator whose oscillation frequency is 4f _SC (=
14.31818MHz). This oscillator (1
The oscillation output of 2a) is output as the second clock signal.
Output to T ₄ . The oscillation output of the oscillator (12A) is supplied to the frequency divider (13a) having a frequency division ratio of 1/33 through the _second signal supply circuit (K ₂ ) and is then frequency-divided. (13
The signal whose frequency is 14.31818 MHz ÷ 35 from a) is supplied to the phase comparator (10a). Further, the oscillation output of the oscillator (5a) is passed through the first signal supply circuit K ₁ , that is, the above-mentioned division ratio is
It is supplied to the phase comparator (10a) through the 1/33 frequency divider (7a) and is phase-compared with the signal from the frequency divider (13a). The ratio of the first sampling frequency 13.5MHz and the second sampling frequency 4f _SC (= 14.31818MHz) is 33:35.
Therefore, the phase is compared by the phase comparator (10a) 13.5M
The frequency of the signal of Hz ÷ 33 and the signal of 14.31818MHz ÷ 35 are equal. The comparison output of the phase comparator (10a) is
It is supplied to the voltage controlled oscillator (12a) as an oscillation frequency control signal through the low pass filter (11a).

According to the clock generation circuit described above, it is possible to obtain the first and second clock signals with high frequency accuracy, and it is possible to reduce conversion noise due to the sampling rate conversion in the sampling rate conversion circuit.
You can make it convenient for adjusting VTRs.

H According to the present invention described above, the lock synchronization of the sampling rate conversion circuit for converting the first digital video signal having the first sampling frequency into the second digital video signal having the second sampling frequency. A circuit,
In a circuit for supplying a synchronization signal of a first digital video signal to generate first and second clock signals having a frequency equal to a first sampling frequency and a second sampling frequency, respectively. The second clock signal can be obtained.

[Brief description of drawings]

1 and 2 are system diagrams showing an embodiment of a clock synchronization circuit of a sampling rate conversion circuit of the present invention, FIG. 3 is a waveform diagram used for the explanation, FIG. 4 is an explanatory diagram of conversion noise, 5 and 6 are configuration diagrams of the sampling rate conversion circuit and its principle diagram, and FIG. 7 is a characteristic diagram of the filter. (1), (3), (3a), (10) and (10a) are phase comparators, (2), (4), (4a), (11) and (11a) are low pass filters and (5). , (5a), (12) and (12a) are voltage controlled oscillators, (6), (7), (7a), (8) and (8
a), (13) and (13a) are frequency dividers, and (9) and (9a) are differentiating circuits.

Claims (3)

(57) [Claims] 1. A clock synchronization circuit of a sampling rate conversion circuit for converting a first digital video signal having a first sampling frequency into a second digital video signal having a second sampling frequency, said clock synchronization circuit comprising: A circuit for supplying a synchronization signal of one digital video signal to generate first and second clock signals having frequencies equal to the first and second sampling frequencies, respectively, which are equal to the first sampling frequency A first variable oscillator having an oscillation frequency, a second variable oscillator having an oscillation frequency equal to the second sampling frequency, a signal related to an oscillation output of the first variable oscillator, and the first digital image A first phase comparator which is supplied with a synchronizing signal for comparison and is compared with both the oscillation outputs of the first and second variable oscillators. , A second phase comparator supplied via the first and second signal supply circuits for comparison, respectively, and the oscillation of the first variable oscillator according to the comparison output of the first phase comparator. The frequency is controlled, and the oscillating frequency of the second variable oscillator is controlled by the comparison output of the second phase comparator. The first and second variable oscillators respectively output the first and second variable oscillators. A clock synchronization circuit of a sampling rate conversion circuit, wherein the first and second clock signals are obtained. 2. The first signal supply circuit has a lock circuit for locking the signal supplied to the second phase comparator with a horizontal synchronizing signal of the first digital video signal. The clock synchronization circuit of the sampling rate conversion circuit according to claim 1. 3. A lock circuit for locking the signal supplied to the second phase comparator with a horizontal synchronizing signal of the first digital video signal, and the lock circuit. 3. The clock synchronization of the sampling rate conversion circuit according to claim 1, further comprising: a changeover switch for selecting a locked or unlocked state by switching the supply and non-supply of the horizontal synchronizing signal with respect to. circuit.