JPS5797142A - Electronic computer system - Google Patents

Electronic computer system

Info

Publication number
JPS5797142A
JPS5797142A JP17166180A JP17166180A JPS5797142A JP S5797142 A JPS5797142 A JP S5797142A JP 17166180 A JP17166180 A JP 17166180A JP 17166180 A JP17166180 A JP 17166180A JP S5797142 A JPS5797142 A JP S5797142A
Authority
JP
Japan
Prior art keywords
control part
memory
mpu31b
microbus
crt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17166180A
Other languages
Japanese (ja)
Inventor
Takashi Mochizuki
Sei Ogiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP17166180A priority Critical patent/JPS5797142A/en
Publication of JPS5797142A publication Critical patent/JPS5797142A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve a display speed, and to lighten a load of a computer, by only designating a picture to be displayed, to a microprocessor, by a CPU, so that a data can be transferred directly between a bulk memory and a CRT control part.
CONSTITUTION: A microprocessor (MPU) 31b and a microbus 31c as well as a refresh memory 31a are provided in a CRT control part 31, so that multi-access can be executed as a bulk memory control part 22x, and also so that the access can be executed from both the CPU13 and the MPU31b by connecting with a memory bus 12 in a computer 1, and the microbus 31c in the CRT control part 31. In this state, the CPU13 gives a CRT display command to the MPU31b, and in accordance with this command, the MPU31b designates an area 21a to be transferred, of a bulk memory 21, to the bulk memory control part 22x. A data of this area is written directly in the refresh memory 31a through the microbus 31c, and is displayed on a monitor part 32.
COPYRIGHT: (C)1982,JPO&Japio
JP17166180A 1980-12-05 1980-12-05 Electronic computer system Pending JPS5797142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17166180A JPS5797142A (en) 1980-12-05 1980-12-05 Electronic computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17166180A JPS5797142A (en) 1980-12-05 1980-12-05 Electronic computer system

Publications (1)

Publication Number Publication Date
JPS5797142A true JPS5797142A (en) 1982-06-16

Family

ID=15927346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17166180A Pending JPS5797142A (en) 1980-12-05 1980-12-05 Electronic computer system

Country Status (1)

Country Link
JP (1) JPS5797142A (en)

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