JPS54139432A - Crt display unit - Google Patents

Crt display unit

Info

Publication number
JPS54139432A
JPS54139432A JP4657678A JP4657678A JPS54139432A JP S54139432 A JPS54139432 A JP S54139432A JP 4657678 A JP4657678 A JP 4657678A JP 4657678 A JP4657678 A JP 4657678A JP S54139432 A JPS54139432 A JP S54139432A
Authority
JP
Japan
Prior art keywords
memory
data
driver
bus
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4657678A
Other languages
Japanese (ja)
Other versions
JPH0227677B2 (en
Inventor
Yasuyo Ishikawa
Kazuo Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4657678A priority Critical patent/JPS54139432A/en
Publication of JPS54139432A publication Critical patent/JPS54139432A/en
Publication of JPH0227677B2 publication Critical patent/JPH0227677B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To avoid the interference for the data of the input source side and the picture element data of the display period by providing the driver to the data bus between the refresh memory and the memory unit plus the input source.
CONSTITUTION: The information to be displayed onto the CRT screen is writtern into refresh memory 6 from the input source such as CPU1 or the like via bus driver 2. RAM15 or ROM is provided to the bus driver in order to increase the functions of the CRT display unit and the microcomputer system. And when the information is transferred between the CPU and memory 15 in the display period, two kinds of information are delivered onto the data bus. Here, bus driver 14 is provided to the data bus which connects CRU1, memory 15 and refresh memory 6, and driver 14 is made inoperative during the display period to isolate between them. As a result, the data interference can be prevented, and also the function can be increased due to installation of memory 15.
COPYRIGHT: (C)1979,JPO&Japio
JP4657678A 1978-04-21 1978-04-21 Crt display unit Granted JPS54139432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4657678A JPS54139432A (en) 1978-04-21 1978-04-21 Crt display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4657678A JPS54139432A (en) 1978-04-21 1978-04-21 Crt display unit

Publications (2)

Publication Number Publication Date
JPS54139432A true JPS54139432A (en) 1979-10-29
JPH0227677B2 JPH0227677B2 (en) 1990-06-19

Family

ID=12751119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4657678A Granted JPS54139432A (en) 1978-04-21 1978-04-21 Crt display unit

Country Status (1)

Country Link
JP (1) JPS54139432A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991559A (en) * 1982-11-17 1984-05-26 Sony Corp Writing circuit of memory
JPS63175892A (en) * 1987-01-16 1988-07-20 三洋電機株式会社 Microcomputer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120629A (en) * 1976-04-05 1977-10-11 Hitachi Ltd Brown tube display control unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120629A (en) * 1976-04-05 1977-10-11 Hitachi Ltd Brown tube display control unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5991559A (en) * 1982-11-17 1984-05-26 Sony Corp Writing circuit of memory
JPH0430052B2 (en) * 1982-11-17 1992-05-20
JPS63175892A (en) * 1987-01-16 1988-07-20 三洋電機株式会社 Microcomputer

Also Published As

Publication number Publication date
JPH0227677B2 (en) 1990-06-19

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