JPS5793731A - Logical level conversion circuit - Google Patents

Logical level conversion circuit

Info

Publication number
JPS5793731A
JPS5793731A JP55170063A JP17006380A JPS5793731A JP S5793731 A JPS5793731 A JP S5793731A JP 55170063 A JP55170063 A JP 55170063A JP 17006380 A JP17006380 A JP 17006380A JP S5793731 A JPS5793731 A JP S5793731A
Authority
JP
Japan
Prior art keywords
drain
gate
source
logical level
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55170063A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0245377B2 (ko
Inventor
Takayoshi Makabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55170063A priority Critical patent/JPS5793731A/ja
Publication of JPS5793731A publication Critical patent/JPS5793731A/ja
Publication of JPH0245377B2 publication Critical patent/JPH0245377B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
JP55170063A 1980-12-02 1980-12-02 Logical level conversion circuit Granted JPS5793731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55170063A JPS5793731A (en) 1980-12-02 1980-12-02 Logical level conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55170063A JPS5793731A (en) 1980-12-02 1980-12-02 Logical level conversion circuit

Publications (2)

Publication Number Publication Date
JPS5793731A true JPS5793731A (en) 1982-06-10
JPH0245377B2 JPH0245377B2 (ko) 1990-10-09

Family

ID=15897936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55170063A Granted JPS5793731A (en) 1980-12-02 1980-12-02 Logical level conversion circuit

Country Status (1)

Country Link
JP (1) JPS5793731A (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4553051A (en) * 1983-07-18 1985-11-12 Texas Instruments Incorporated PMOS Input buffer compatible with logic inputs from an NMOS microprocessor
EP0220833A2 (en) * 1985-09-24 1987-05-06 Kabushiki Kaisha Toshiba Level conversion circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4553051A (en) * 1983-07-18 1985-11-12 Texas Instruments Incorporated PMOS Input buffer compatible with logic inputs from an NMOS microprocessor
EP0220833A2 (en) * 1985-09-24 1987-05-06 Kabushiki Kaisha Toshiba Level conversion circuit

Also Published As

Publication number Publication date
JPH0245377B2 (ko) 1990-10-09

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