JPS5752225A - Level converting circuit - Google Patents
Level converting circuitInfo
- Publication number
- JPS5752225A JPS5752225A JP55126521A JP12652180A JPS5752225A JP S5752225 A JPS5752225 A JP S5752225A JP 55126521 A JP55126521 A JP 55126521A JP 12652180 A JP12652180 A JP 12652180A JP S5752225 A JPS5752225 A JP S5752225A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- gate
- reverse
- converting circuit
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To decrease the number of elements, by connecting the first polarity transistor which has connected an output of the low voltage side and the reverse potential to the source and the gate, respectively, to the second polarity transistor, in a level converting circuit consisting of an IGFET. CONSTITUTION:In a level converting circuit consisting of an IGFET, reverse output potential V1 of the low voltage side by an inverter 21 is inputted directly to a P channel transistor TR24, also is inputted to a gate Vi of an N channel TR25 which has been by-passed to source potential VSS by a resister 23 through a capacity 22, and each drain of the trasistors 24, 25 is connected to each other and outputs voltage V0. Moreover, the reverse voltage V1 and the voltage V0 are connected to the source of a P channel TR26 and the gate, respectively, and its drain is connected to the gate of the transistor 25. Accordingly, since the TRs 24, 25 execute a push- pull operation to each other, the power consumption is reduced, and furthermore, when the reverse voltage V1 has become high voltage VDD as a direct current, the voltage V0 is set to the source potential VSS stably.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55126521A JPS5752225A (en) | 1980-09-11 | 1980-09-11 | Level converting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55126521A JPS5752225A (en) | 1980-09-11 | 1980-09-11 | Level converting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5752225A true JPS5752225A (en) | 1982-03-27 |
Family
ID=14937258
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55126521A Pending JPS5752225A (en) | 1980-09-11 | 1980-09-11 | Level converting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5752225A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5467363A (en) * | 1977-11-08 | 1979-05-30 | Sharp Corp | C-mos circuit of high voltage operation |
-
1980
- 1980-09-11 JP JP55126521A patent/JPS5752225A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5467363A (en) * | 1977-11-08 | 1979-05-30 | Sharp Corp | C-mos circuit of high voltage operation |
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